624 lines
15 KiB
C
624 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/**
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* Test driver to test endpoint functionality
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*
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*/
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#include <linux/crc32.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/pci_ids.h>
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#include <linux/random.h>
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#include <linux/pci-epc.h>
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#include <linux/pci-epf.h>
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#include <linux/pci_regs.h>
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#define IRQ_TYPE_LEGACY 0
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#define IRQ_TYPE_MSI 1
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#define IRQ_TYPE_MSIX 2
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#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
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#define COMMAND_RAISE_MSI_IRQ BIT(1)
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#define COMMAND_RAISE_MSIX_IRQ BIT(2)
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#define COMMAND_READ BIT(3)
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#define COMMAND_WRITE BIT(4)
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#define COMMAND_COPY BIT(5)
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#define STATUS_READ_SUCCESS BIT(0)
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#define STATUS_READ_FAIL BIT(1)
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#define STATUS_WRITE_SUCCESS BIT(2)
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#define STATUS_WRITE_FAIL BIT(3)
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#define STATUS_COPY_SUCCESS BIT(4)
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#define STATUS_COPY_FAIL BIT(5)
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#define STATUS_IRQ_RAISED BIT(6)
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#define STATUS_SRC_ADDR_INVALID BIT(7)
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#define STATUS_DST_ADDR_INVALID BIT(8)
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#define TIMER_RESOLUTION 1
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static struct workqueue_struct *kpcitest_workqueue;
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struct pci_epf_test {
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void *reg[6];
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struct pci_epf *epf;
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enum pci_barno test_reg_bar;
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struct delayed_work cmd_handler;
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const struct pci_epc_features *epc_features;
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};
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struct pci_epf_test_reg {
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u32 magic;
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u32 command;
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u32 status;
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u64 src_addr;
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u64 dst_addr;
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u32 size;
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u32 checksum;
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u32 irq_type;
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u32 irq_number;
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} __packed;
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static struct pci_epf_header test_header = {
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.vendorid = PCI_ANY_ID,
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.deviceid = PCI_ANY_ID,
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.baseclass_code = PCI_CLASS_OTHERS,
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.interrupt_pin = PCI_INTERRUPT_INTA,
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};
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static size_t bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
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static int pci_epf_test_copy(struct pci_epf_test *epf_test)
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{
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int ret;
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void __iomem *src_addr;
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void __iomem *dst_addr;
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phys_addr_t src_phys_addr;
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phys_addr_t dst_phys_addr;
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struct pci_epf *epf = epf_test->epf;
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struct device *dev = &epf->dev;
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struct pci_epc *epc = epf->epc;
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enum pci_barno test_reg_bar = epf_test->test_reg_bar;
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struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
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src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size);
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if (!src_addr) {
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dev_err(dev, "Failed to allocate source address\n");
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reg->status = STATUS_SRC_ADDR_INVALID;
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ret = -ENOMEM;
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goto err;
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}
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ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, reg->src_addr,
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reg->size);
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if (ret) {
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dev_err(dev, "Failed to map source address\n");
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reg->status = STATUS_SRC_ADDR_INVALID;
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goto err_src_addr;
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}
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dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size);
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if (!dst_addr) {
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dev_err(dev, "Failed to allocate destination address\n");
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reg->status = STATUS_DST_ADDR_INVALID;
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ret = -ENOMEM;
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goto err_src_map_addr;
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}
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ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, reg->dst_addr,
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reg->size);
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if (ret) {
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dev_err(dev, "Failed to map destination address\n");
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reg->status = STATUS_DST_ADDR_INVALID;
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goto err_dst_addr;
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}
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memcpy(dst_addr, src_addr, reg->size);
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pci_epc_unmap_addr(epc, epf->func_no, dst_phys_addr);
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err_dst_addr:
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pci_epc_mem_free_addr(epc, dst_phys_addr, dst_addr, reg->size);
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err_src_map_addr:
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pci_epc_unmap_addr(epc, epf->func_no, src_phys_addr);
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err_src_addr:
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pci_epc_mem_free_addr(epc, src_phys_addr, src_addr, reg->size);
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err:
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return ret;
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}
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static int pci_epf_test_read(struct pci_epf_test *epf_test)
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{
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int ret;
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void __iomem *src_addr;
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void *buf;
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u32 crc32;
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phys_addr_t phys_addr;
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struct pci_epf *epf = epf_test->epf;
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struct device *dev = &epf->dev;
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struct pci_epc *epc = epf->epc;
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enum pci_barno test_reg_bar = epf_test->test_reg_bar;
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struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
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src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
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if (!src_addr) {
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dev_err(dev, "Failed to allocate address\n");
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reg->status = STATUS_SRC_ADDR_INVALID;
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ret = -ENOMEM;
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goto err;
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}
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ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->src_addr,
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reg->size);
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if (ret) {
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dev_err(dev, "Failed to map address\n");
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reg->status = STATUS_SRC_ADDR_INVALID;
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goto err_addr;
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}
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buf = kzalloc(reg->size, GFP_KERNEL);
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if (!buf) {
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ret = -ENOMEM;
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goto err_map_addr;
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}
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memcpy_fromio(buf, src_addr, reg->size);
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crc32 = crc32_le(~0, buf, reg->size);
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if (crc32 != reg->checksum)
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ret = -EIO;
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kfree(buf);
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err_map_addr:
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pci_epc_unmap_addr(epc, epf->func_no, phys_addr);
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err_addr:
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pci_epc_mem_free_addr(epc, phys_addr, src_addr, reg->size);
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err:
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return ret;
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}
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static int pci_epf_test_write(struct pci_epf_test *epf_test)
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{
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int ret;
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void __iomem *dst_addr;
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void *buf;
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phys_addr_t phys_addr;
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struct pci_epf *epf = epf_test->epf;
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struct device *dev = &epf->dev;
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struct pci_epc *epc = epf->epc;
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enum pci_barno test_reg_bar = epf_test->test_reg_bar;
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struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
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dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
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if (!dst_addr) {
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dev_err(dev, "Failed to allocate address\n");
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reg->status = STATUS_DST_ADDR_INVALID;
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ret = -ENOMEM;
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goto err;
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}
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ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->dst_addr,
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reg->size);
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if (ret) {
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dev_err(dev, "Failed to map address\n");
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reg->status = STATUS_DST_ADDR_INVALID;
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goto err_addr;
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}
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buf = kzalloc(reg->size, GFP_KERNEL);
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if (!buf) {
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ret = -ENOMEM;
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goto err_map_addr;
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}
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get_random_bytes(buf, reg->size);
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reg->checksum = crc32_le(~0, buf, reg->size);
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memcpy_toio(dst_addr, buf, reg->size);
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/*
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* wait 1ms inorder for the write to complete. Without this delay L3
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* error in observed in the host system.
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*/
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usleep_range(1000, 2000);
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kfree(buf);
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err_map_addr:
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pci_epc_unmap_addr(epc, epf->func_no, phys_addr);
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err_addr:
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pci_epc_mem_free_addr(epc, phys_addr, dst_addr, reg->size);
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err:
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return ret;
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}
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static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq_type,
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u16 irq)
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{
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struct pci_epf *epf = epf_test->epf;
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struct device *dev = &epf->dev;
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struct pci_epc *epc = epf->epc;
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enum pci_barno test_reg_bar = epf_test->test_reg_bar;
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struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
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reg->status |= STATUS_IRQ_RAISED;
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switch (irq_type) {
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case IRQ_TYPE_LEGACY:
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pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0);
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break;
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case IRQ_TYPE_MSI:
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pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, irq);
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break;
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case IRQ_TYPE_MSIX:
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pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSIX, irq);
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break;
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default:
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dev_err(dev, "Failed to raise IRQ, unknown type\n");
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break;
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}
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}
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static void pci_epf_test_cmd_handler(struct work_struct *work)
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{
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int ret;
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int count;
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u32 command;
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struct pci_epf_test *epf_test = container_of(work, struct pci_epf_test,
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cmd_handler.work);
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struct pci_epf *epf = epf_test->epf;
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struct device *dev = &epf->dev;
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struct pci_epc *epc = epf->epc;
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enum pci_barno test_reg_bar = epf_test->test_reg_bar;
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struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
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command = reg->command;
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if (!command)
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goto reset_handler;
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reg->command = 0;
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reg->status = 0;
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if (reg->irq_type > IRQ_TYPE_MSIX) {
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dev_err(dev, "Failed to detect IRQ type\n");
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goto reset_handler;
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}
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if (command & COMMAND_RAISE_LEGACY_IRQ) {
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reg->status = STATUS_IRQ_RAISED;
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pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0);
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goto reset_handler;
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}
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if (command & COMMAND_WRITE) {
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ret = pci_epf_test_write(epf_test);
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if (ret)
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reg->status |= STATUS_WRITE_FAIL;
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else
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reg->status |= STATUS_WRITE_SUCCESS;
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pci_epf_test_raise_irq(epf_test, reg->irq_type,
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reg->irq_number);
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goto reset_handler;
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}
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if (command & COMMAND_READ) {
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ret = pci_epf_test_read(epf_test);
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if (!ret)
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reg->status |= STATUS_READ_SUCCESS;
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else
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reg->status |= STATUS_READ_FAIL;
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pci_epf_test_raise_irq(epf_test, reg->irq_type,
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reg->irq_number);
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goto reset_handler;
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}
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if (command & COMMAND_COPY) {
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ret = pci_epf_test_copy(epf_test);
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if (!ret)
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reg->status |= STATUS_COPY_SUCCESS;
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else
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reg->status |= STATUS_COPY_FAIL;
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pci_epf_test_raise_irq(epf_test, reg->irq_type,
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reg->irq_number);
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goto reset_handler;
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}
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if (command & COMMAND_RAISE_MSI_IRQ) {
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count = pci_epc_get_msi(epc, epf->func_no);
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if (reg->irq_number > count || count <= 0)
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goto reset_handler;
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reg->status = STATUS_IRQ_RAISED;
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pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI,
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reg->irq_number);
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goto reset_handler;
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}
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if (command & COMMAND_RAISE_MSIX_IRQ) {
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count = pci_epc_get_msix(epc, epf->func_no);
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if (reg->irq_number > count || count <= 0)
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goto reset_handler;
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reg->status = STATUS_IRQ_RAISED;
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pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSIX,
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reg->irq_number);
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goto reset_handler;
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}
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reset_handler:
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queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
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msecs_to_jiffies(1));
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}
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static void pci_epf_test_linkup(struct pci_epf *epf)
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{
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struct pci_epf_test *epf_test = epf_get_drvdata(epf);
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queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
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msecs_to_jiffies(1));
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}
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static void pci_epf_test_unbind(struct pci_epf *epf)
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{
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struct pci_epf_test *epf_test = epf_get_drvdata(epf);
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struct pci_epc *epc = epf->epc;
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struct pci_epf_bar *epf_bar;
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int bar;
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cancel_delayed_work(&epf_test->cmd_handler);
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pci_epc_stop(epc);
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for (bar = BAR_0; bar <= BAR_5; bar++) {
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epf_bar = &epf->bar[bar];
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if (epf_test->reg[bar]) {
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pci_epc_clear_bar(epc, epf->func_no, epf_bar);
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pci_epf_free_space(epf, epf_test->reg[bar], bar);
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}
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}
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}
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static int pci_epf_test_set_bar(struct pci_epf *epf)
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{
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int bar, add;
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int ret;
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struct pci_epf_bar *epf_bar;
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struct pci_epc *epc = epf->epc;
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struct device *dev = &epf->dev;
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struct pci_epf_test *epf_test = epf_get_drvdata(epf);
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enum pci_barno test_reg_bar = epf_test->test_reg_bar;
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const struct pci_epc_features *epc_features;
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epc_features = epf_test->epc_features;
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for (bar = BAR_0; bar <= BAR_5; bar += add) {
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epf_bar = &epf->bar[bar];
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/*
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* pci_epc_set_bar() sets PCI_BASE_ADDRESS_MEM_TYPE_64
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* if the specific implementation required a 64-bit BAR,
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* even if we only requested a 32-bit BAR.
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*/
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add = (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ? 2 : 1;
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if (!!(epc_features->reserved_bar & (1 << bar)))
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continue;
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ret = pci_epc_set_bar(epc, epf->func_no, epf_bar);
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if (ret) {
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pci_epf_free_space(epf, epf_test->reg[bar], bar);
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dev_err(dev, "Failed to set BAR%d\n", bar);
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if (bar == test_reg_bar)
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return ret;
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}
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}
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return 0;
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}
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static int pci_epf_test_alloc_space(struct pci_epf *epf)
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{
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struct pci_epf_test *epf_test = epf_get_drvdata(epf);
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struct device *dev = &epf->dev;
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struct pci_epf_bar *epf_bar;
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void *base;
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int bar, add;
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enum pci_barno test_reg_bar = epf_test->test_reg_bar;
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const struct pci_epc_features *epc_features;
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size_t test_reg_size;
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epc_features = epf_test->epc_features;
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if (epc_features->bar_fixed_size[test_reg_bar])
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test_reg_size = bar_size[test_reg_bar];
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else
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test_reg_size = sizeof(struct pci_epf_test_reg);
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base = pci_epf_alloc_space(epf, test_reg_size,
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test_reg_bar, epc_features->align);
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if (!base) {
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dev_err(dev, "Failed to allocated register space\n");
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return -ENOMEM;
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}
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epf_test->reg[test_reg_bar] = base;
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for (bar = BAR_0; bar <= BAR_5; bar += add) {
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epf_bar = &epf->bar[bar];
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add = (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ? 2 : 1;
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if (bar == test_reg_bar)
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continue;
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if (!!(epc_features->reserved_bar & (1 << bar)))
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continue;
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base = pci_epf_alloc_space(epf, bar_size[bar], bar,
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epc_features->align);
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if (!base)
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dev_err(dev, "Failed to allocate space for BAR%d\n",
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bar);
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epf_test->reg[bar] = base;
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}
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return 0;
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}
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static void pci_epf_configure_bar(struct pci_epf *epf,
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const struct pci_epc_features *epc_features)
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{
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struct pci_epf_bar *epf_bar;
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bool bar_fixed_64bit;
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int i;
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for (i = BAR_0; i <= BAR_5; i++) {
|
|
epf_bar = &epf->bar[i];
|
|
bar_fixed_64bit = !!(epc_features->bar_fixed_64bit & (1 << i));
|
|
if (bar_fixed_64bit)
|
|
epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
|
|
if (epc_features->bar_fixed_size[i])
|
|
bar_size[i] = epc_features->bar_fixed_size[i];
|
|
}
|
|
}
|
|
|
|
static int pci_epf_test_bind(struct pci_epf *epf)
|
|
{
|
|
int ret;
|
|
struct pci_epf_test *epf_test = epf_get_drvdata(epf);
|
|
struct pci_epf_header *header = epf->header;
|
|
const struct pci_epc_features *epc_features;
|
|
enum pci_barno test_reg_bar = BAR_0;
|
|
struct pci_epc *epc = epf->epc;
|
|
struct device *dev = &epf->dev;
|
|
bool linkup_notifier = false;
|
|
bool msix_capable = false;
|
|
bool msi_capable = true;
|
|
|
|
if (WARN_ON_ONCE(!epc))
|
|
return -EINVAL;
|
|
|
|
epc_features = pci_epc_get_features(epc, epf->func_no);
|
|
if (epc_features) {
|
|
linkup_notifier = epc_features->linkup_notifier;
|
|
msix_capable = epc_features->msix_capable;
|
|
msi_capable = epc_features->msi_capable;
|
|
test_reg_bar = pci_epc_get_first_free_bar(epc_features);
|
|
pci_epf_configure_bar(epf, epc_features);
|
|
}
|
|
|
|
epf_test->test_reg_bar = test_reg_bar;
|
|
epf_test->epc_features = epc_features;
|
|
|
|
ret = pci_epc_write_header(epc, epf->func_no, header);
|
|
if (ret) {
|
|
dev_err(dev, "Configuration header write failed\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = pci_epf_test_alloc_space(epf);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = pci_epf_test_set_bar(epf);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (msi_capable) {
|
|
ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
|
|
if (ret) {
|
|
dev_err(dev, "MSI configuration failed\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (msix_capable) {
|
|
ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts);
|
|
if (ret) {
|
|
dev_err(dev, "MSI-X configuration failed\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (!linkup_notifier)
|
|
queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pci_epf_device_id pci_epf_test_ids[] = {
|
|
{
|
|
.name = "pci_epf_test",
|
|
},
|
|
{},
|
|
};
|
|
|
|
static int pci_epf_test_probe(struct pci_epf *epf)
|
|
{
|
|
struct pci_epf_test *epf_test;
|
|
struct device *dev = &epf->dev;
|
|
|
|
epf_test = devm_kzalloc(dev, sizeof(*epf_test), GFP_KERNEL);
|
|
if (!epf_test)
|
|
return -ENOMEM;
|
|
|
|
epf->header = &test_header;
|
|
epf_test->epf = epf;
|
|
|
|
INIT_DELAYED_WORK(&epf_test->cmd_handler, pci_epf_test_cmd_handler);
|
|
|
|
epf_set_drvdata(epf, epf_test);
|
|
return 0;
|
|
}
|
|
|
|
static struct pci_epf_ops ops = {
|
|
.unbind = pci_epf_test_unbind,
|
|
.bind = pci_epf_test_bind,
|
|
.linkup = pci_epf_test_linkup,
|
|
};
|
|
|
|
static struct pci_epf_driver test_driver = {
|
|
.driver.name = "pci_epf_test",
|
|
.probe = pci_epf_test_probe,
|
|
.id_table = pci_epf_test_ids,
|
|
.ops = &ops,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static int __init pci_epf_test_init(void)
|
|
{
|
|
int ret;
|
|
|
|
kpcitest_workqueue = alloc_workqueue("kpcitest",
|
|
WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
|
|
if (!kpcitest_workqueue) {
|
|
pr_err("Failed to allocate the kpcitest work queue\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ret = pci_epf_register_driver(&test_driver);
|
|
if (ret) {
|
|
pr_err("Failed to register pci epf test driver --> %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
module_init(pci_epf_test_init);
|
|
|
|
static void __exit pci_epf_test_exit(void)
|
|
{
|
|
pci_epf_unregister_driver(&test_driver);
|
|
}
|
|
module_exit(pci_epf_test_exit);
|
|
|
|
MODULE_DESCRIPTION("PCI EPF TEST DRIVER");
|
|
MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
|
|
MODULE_LICENSE("GPL v2");
|