605 lines
14 KiB
C
605 lines
14 KiB
C
/*
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* Copyright (C) 2003 Rick Bronson
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*
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* Derived from drivers/mtd/nand/autcpu12.c
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* Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
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*
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* Derived from drivers/mtd/spia.c
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* Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
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*
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*
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* Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
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* Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
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*
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* Derived from Das U-Boot source code
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* (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
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* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <mach/board.h>
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#include <mach/cpu.h>
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#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
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#define hard_ecc 1
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#else
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#define hard_ecc 0
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#endif
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#ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
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#define no_ecc 1
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#else
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#define no_ecc 0
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#endif
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/* Register access macros */
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#define ecc_readl(add, reg) \
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__raw_readl(add + ATMEL_ECC_##reg)
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#define ecc_writel(add, reg, value) \
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__raw_writel((value), add + ATMEL_ECC_##reg)
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#include "atmel_nand_ecc.h" /* Hardware ECC registers */
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/* oob layout for large page size
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* bad block info is on bytes 0 and 1
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* the bytes have to be consecutives to avoid
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* several NAND_CMD_RNDOUT during read
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*/
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static struct nand_ecclayout atmel_oobinfo_large = {
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.eccbytes = 4,
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.eccpos = {60, 61, 62, 63},
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.oobfree = {
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{2, 58}
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},
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};
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/* oob layout for small page size
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* bad block info is on bytes 4 and 5
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* the bytes have to be consecutives to avoid
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* several NAND_CMD_RNDOUT during read
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*/
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static struct nand_ecclayout atmel_oobinfo_small = {
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.eccbytes = 4,
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.eccpos = {0, 1, 2, 3},
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.oobfree = {
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{6, 10}
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},
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};
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struct atmel_nand_host {
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struct nand_chip nand_chip;
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struct mtd_info mtd;
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void __iomem *io_base;
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struct atmel_nand_data *board;
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struct device *dev;
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void __iomem *ecc;
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};
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/*
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* Enable NAND.
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*/
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static void atmel_nand_enable(struct atmel_nand_host *host)
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{
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if (host->board->enable_pin)
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gpio_set_value(host->board->enable_pin, 0);
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}
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/*
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* Disable NAND.
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*/
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static void atmel_nand_disable(struct atmel_nand_host *host)
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{
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if (host->board->enable_pin)
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gpio_set_value(host->board->enable_pin, 1);
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}
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/*
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* Hardware specific access to control-lines
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*/
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static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct atmel_nand_host *host = nand_chip->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_NCE)
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atmel_nand_enable(host);
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else
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atmel_nand_disable(host);
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}
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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writeb(cmd, host->io_base + (1 << host->board->cle));
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else
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writeb(cmd, host->io_base + (1 << host->board->ale));
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}
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/*
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* Read the Device Ready pin.
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*/
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static int atmel_nand_device_ready(struct mtd_info *mtd)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct atmel_nand_host *host = nand_chip->priv;
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return gpio_get_value(host->board->rdy_pin);
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}
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/*
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* Minimal-overhead PIO for data access.
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*/
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static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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__raw_readsb(nand_chip->IO_ADDR_R, buf, len);
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}
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static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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__raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
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}
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static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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__raw_writesb(nand_chip->IO_ADDR_W, buf, len);
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}
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static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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__raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
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}
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/*
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* Calculate HW ECC
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*
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* function called after a write
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*
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* mtd: MTD block structure
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* dat: raw data (unused)
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* ecc_code: buffer for ECC
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*/
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static int atmel_nand_calculate(struct mtd_info *mtd,
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const u_char *dat, unsigned char *ecc_code)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct atmel_nand_host *host = nand_chip->priv;
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uint32_t *eccpos = nand_chip->ecc.layout->eccpos;
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unsigned int ecc_value;
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/* get the first 2 ECC bytes */
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ecc_value = ecc_readl(host->ecc, PR);
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ecc_code[0] = ecc_value & 0xFF;
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ecc_code[1] = (ecc_value >> 8) & 0xFF;
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/* get the last 2 ECC bytes */
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ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
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ecc_code[2] = ecc_value & 0xFF;
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ecc_code[3] = (ecc_value >> 8) & 0xFF;
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return 0;
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}
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/*
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* HW ECC read page function
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*
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* mtd: mtd info structure
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* chip: nand chip info structure
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* buf: buffer to store read data
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*/
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static int atmel_nand_read_page(struct mtd_info *mtd,
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struct nand_chip *chip, uint8_t *buf)
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{
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int eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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uint32_t *eccpos = chip->ecc.layout->eccpos;
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uint8_t *p = buf;
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uint8_t *oob = chip->oob_poi;
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uint8_t *ecc_pos;
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int stat;
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/*
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* Errata: ALE is incorrectly wired up to the ECC controller
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* on the AP7000, so it will include the address cycles in the
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* ECC calculation.
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*
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* Workaround: Reset the parity registers before reading the
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* actual data.
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*/
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if (cpu_is_at32ap7000()) {
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struct atmel_nand_host *host = chip->priv;
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ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
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}
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/* read the page */
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chip->read_buf(mtd, p, eccsize);
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/* move to ECC position if needed */
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if (eccpos[0] != 0) {
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/* This only works on large pages
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* because the ECC controller waits for
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* NAND_CMD_RNDOUTSTART after the
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* NAND_CMD_RNDOUT.
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* anyway, for small pages, the eccpos[0] == 0
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*/
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chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
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mtd->writesize + eccpos[0], -1);
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}
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/* the ECC controller needs to read the ECC just after the data */
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ecc_pos = oob + eccpos[0];
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chip->read_buf(mtd, ecc_pos, eccbytes);
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/* check if there's an error */
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stat = chip->ecc.correct(mtd, p, oob, NULL);
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if (stat < 0)
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mtd->ecc_stats.failed++;
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else
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mtd->ecc_stats.corrected += stat;
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/* get back to oob start (end of page) */
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chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
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/* read the oob */
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chip->read_buf(mtd, oob, mtd->oobsize);
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return 0;
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}
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/*
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* HW ECC Correction
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*
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* function called after a read
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*
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* mtd: MTD block structure
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* dat: raw data read from the chip
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* read_ecc: ECC from the chip (unused)
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* isnull: unused
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*
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* Detect and correct a 1 bit error for a page
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*/
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static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *isnull)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct atmel_nand_host *host = nand_chip->priv;
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unsigned int ecc_status;
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unsigned int ecc_word, ecc_bit;
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/* get the status from the Status Register */
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ecc_status = ecc_readl(host->ecc, SR);
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/* if there's no error */
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if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
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return 0;
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/* get error bit offset (4 bits) */
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ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
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/* get word address (12 bits) */
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ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
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ecc_word >>= 4;
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/* if there are multiple errors */
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if (ecc_status & ATMEL_ECC_MULERR) {
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/* check if it is a freshly erased block
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* (filled with 0xff) */
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if ((ecc_bit == ATMEL_ECC_BITADDR)
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&& (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
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/* the block has just been erased, return OK */
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return 0;
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}
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/* it doesn't seems to be a freshly
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* erased block.
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* We can't correct so many errors */
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dev_dbg(host->dev, "atmel_nand : multiple errors detected."
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" Unable to correct.\n");
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return -EIO;
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}
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/* if there's a single bit error : we can correct it */
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if (ecc_status & ATMEL_ECC_ECCERR) {
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/* there's nothing much to do here.
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* the bit error is on the ECC itself.
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*/
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dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
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" Nothing to correct\n");
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return 0;
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}
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dev_dbg(host->dev, "atmel_nand : one bit error on data."
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" (word offset in the page :"
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" 0x%x bit offset : 0x%x)\n",
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ecc_word, ecc_bit);
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/* correct the error */
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if (nand_chip->options & NAND_BUSWIDTH_16) {
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/* 16 bits words */
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((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
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} else {
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/* 8 bits words */
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dat[ecc_word] ^= (1 << ecc_bit);
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}
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dev_dbg(host->dev, "atmel_nand : error corrected\n");
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return 1;
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}
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/*
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* Enable HW ECC : unused on most chips
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*/
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static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
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{
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if (cpu_is_at32ap7000()) {
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struct nand_chip *nand_chip = mtd->priv;
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struct atmel_nand_host *host = nand_chip->priv;
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ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
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}
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}
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#ifdef CONFIG_MTD_PARTITIONS
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static const char *part_probes[] = { "cmdlinepart", NULL };
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#endif
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/*
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* Probe for the NAND device.
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*/
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static int __init atmel_nand_probe(struct platform_device *pdev)
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{
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struct atmel_nand_host *host;
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struct mtd_info *mtd;
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struct nand_chip *nand_chip;
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struct resource *regs;
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struct resource *mem;
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int res;
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#ifdef CONFIG_MTD_PARTITIONS
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struct mtd_partition *partitions = NULL;
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int num_partitions = 0;
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#endif
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem) {
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printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
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return -ENXIO;
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}
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/* Allocate memory for the device structure (and zero it) */
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host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
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if (!host) {
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printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
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return -ENOMEM;
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}
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host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
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if (host->io_base == NULL) {
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printk(KERN_ERR "atmel_nand: ioremap failed\n");
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res = -EIO;
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goto err_nand_ioremap;
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}
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mtd = &host->mtd;
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nand_chip = &host->nand_chip;
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host->board = pdev->dev.platform_data;
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host->dev = &pdev->dev;
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nand_chip->priv = host; /* link the private data structures */
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mtd->priv = nand_chip;
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mtd->owner = THIS_MODULE;
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/* Set address of NAND IO lines */
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nand_chip->IO_ADDR_R = host->io_base;
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nand_chip->IO_ADDR_W = host->io_base;
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nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
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if (host->board->rdy_pin)
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nand_chip->dev_ready = atmel_nand_device_ready;
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!regs && hard_ecc) {
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printk(KERN_ERR "atmel_nand: can't get I/O resource "
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"regs\nFalling back on software ECC\n");
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}
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nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
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if (no_ecc)
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nand_chip->ecc.mode = NAND_ECC_NONE;
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if (hard_ecc && regs) {
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host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
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if (host->ecc == NULL) {
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printk(KERN_ERR "atmel_nand: ioremap failed\n");
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res = -EIO;
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goto err_ecc_ioremap;
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}
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nand_chip->ecc.mode = NAND_ECC_HW;
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nand_chip->ecc.calculate = atmel_nand_calculate;
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nand_chip->ecc.correct = atmel_nand_correct;
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nand_chip->ecc.hwctl = atmel_nand_hwctl;
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nand_chip->ecc.read_page = atmel_nand_read_page;
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nand_chip->ecc.bytes = 4;
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}
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nand_chip->chip_delay = 20; /* 20us command delay time */
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if (host->board->bus_width_16) { /* 16-bit bus width */
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nand_chip->options |= NAND_BUSWIDTH_16;
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nand_chip->read_buf = atmel_read_buf16;
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nand_chip->write_buf = atmel_write_buf16;
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} else {
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nand_chip->read_buf = atmel_read_buf;
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nand_chip->write_buf = atmel_write_buf;
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}
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platform_set_drvdata(pdev, host);
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atmel_nand_enable(host);
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if (host->board->det_pin) {
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if (gpio_get_value(host->board->det_pin)) {
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printk("No SmartMedia card inserted.\n");
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res = ENXIO;
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goto err_no_card;
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}
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}
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/* first scan to find the device and get the page size */
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if (nand_scan_ident(mtd, 1)) {
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res = -ENXIO;
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goto err_scan_ident;
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}
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if (nand_chip->ecc.mode == NAND_ECC_HW) {
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/* ECC is calculated for the whole page (1 step) */
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nand_chip->ecc.size = mtd->writesize;
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/* set ECC page size and oob layout */
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switch (mtd->writesize) {
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case 512:
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nand_chip->ecc.layout = &atmel_oobinfo_small;
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ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
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break;
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case 1024:
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nand_chip->ecc.layout = &atmel_oobinfo_large;
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ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
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break;
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case 2048:
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nand_chip->ecc.layout = &atmel_oobinfo_large;
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ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
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break;
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case 4096:
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nand_chip->ecc.layout = &atmel_oobinfo_large;
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ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
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break;
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default:
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|
/* page size not handled by HW ECC */
|
|
/* switching back to soft ECC */
|
|
nand_chip->ecc.mode = NAND_ECC_SOFT;
|
|
nand_chip->ecc.calculate = NULL;
|
|
nand_chip->ecc.correct = NULL;
|
|
nand_chip->ecc.hwctl = NULL;
|
|
nand_chip->ecc.read_page = NULL;
|
|
nand_chip->ecc.postpad = 0;
|
|
nand_chip->ecc.prepad = 0;
|
|
nand_chip->ecc.bytes = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* second phase scan */
|
|
if (nand_scan_tail(mtd)) {
|
|
res = -ENXIO;
|
|
goto err_scan_tail;
|
|
}
|
|
|
|
#ifdef CONFIG_MTD_PARTITIONS
|
|
#ifdef CONFIG_MTD_CMDLINE_PARTS
|
|
mtd->name = "atmel_nand";
|
|
num_partitions = parse_mtd_partitions(mtd, part_probes,
|
|
&partitions, 0);
|
|
#endif
|
|
if (num_partitions <= 0 && host->board->partition_info)
|
|
partitions = host->board->partition_info(mtd->size,
|
|
&num_partitions);
|
|
|
|
if ((!partitions) || (num_partitions == 0)) {
|
|
printk(KERN_ERR "atmel_nand: No parititions defined, or unsupported device.\n");
|
|
res = ENXIO;
|
|
goto err_no_partitions;
|
|
}
|
|
|
|
res = add_mtd_partitions(mtd, partitions, num_partitions);
|
|
#else
|
|
res = add_mtd_device(mtd);
|
|
#endif
|
|
|
|
if (!res)
|
|
return res;
|
|
|
|
#ifdef CONFIG_MTD_PARTITIONS
|
|
err_no_partitions:
|
|
#endif
|
|
nand_release(mtd);
|
|
err_scan_tail:
|
|
err_scan_ident:
|
|
err_no_card:
|
|
atmel_nand_disable(host);
|
|
platform_set_drvdata(pdev, NULL);
|
|
if (host->ecc)
|
|
iounmap(host->ecc);
|
|
err_ecc_ioremap:
|
|
iounmap(host->io_base);
|
|
err_nand_ioremap:
|
|
kfree(host);
|
|
return res;
|
|
}
|
|
|
|
/*
|
|
* Remove a NAND device.
|
|
*/
|
|
static int __exit atmel_nand_remove(struct platform_device *pdev)
|
|
{
|
|
struct atmel_nand_host *host = platform_get_drvdata(pdev);
|
|
struct mtd_info *mtd = &host->mtd;
|
|
|
|
nand_release(mtd);
|
|
|
|
atmel_nand_disable(host);
|
|
|
|
if (host->ecc)
|
|
iounmap(host->ecc);
|
|
iounmap(host->io_base);
|
|
kfree(host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver atmel_nand_driver = {
|
|
.remove = __exit_p(atmel_nand_remove),
|
|
.driver = {
|
|
.name = "atmel_nand",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init atmel_nand_init(void)
|
|
{
|
|
return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
|
|
}
|
|
|
|
|
|
static void __exit atmel_nand_exit(void)
|
|
{
|
|
platform_driver_unregister(&atmel_nand_driver);
|
|
}
|
|
|
|
|
|
module_init(atmel_nand_init);
|
|
module_exit(atmel_nand_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Rick Bronson");
|
|
MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
|
|
MODULE_ALIAS("platform:atmel_nand");
|