31 lines
1.1 KiB
C
31 lines
1.1 KiB
C
/*
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* Copyright (C) 2003-2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#ifndef MSI_H
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#define MSI_H
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#define PCI_MSIX_ENTRY_SIZE 16
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#define PCI_MSIX_ENTRY_LOWER_ADDR 0
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#define PCI_MSIX_ENTRY_UPPER_ADDR 4
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#define PCI_MSIX_ENTRY_DATA 8
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#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
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#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
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#define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
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#define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
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#define msi_data_reg(base, is64bit) \
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(base + ((is64bit == 1) ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32))
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#define msi_mask_reg(base, is64bit) \
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(base + ((is64bit == 1) ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32))
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#define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT))
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#define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT))
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#define msix_table_offset_reg(base) (base + PCI_MSIX_TABLE)
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#define msix_pba_offset_reg(base) (base + PCI_MSIX_PBA)
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#define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
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#define multi_msix_capable(control) msix_table_size((control))
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#endif /* MSI_H */
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