415 lines
10 KiB
C
415 lines
10 KiB
C
/*
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* Driver for the ST Microelectronics SPEAr pinmux
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*
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* Copyright (C) 2012 ST Microelectronics
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* Viresh Kumar <vireshk@kernel.org>
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*
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* Inspired from:
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* - U300 Pinctl drivers
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* - Tegra Pinctl drivers
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_gpio.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "pinctrl-spear.h"
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#define DRIVER_NAME "spear-pinmux"
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static void muxregs_endisable(struct spear_pmx *pmx,
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struct spear_muxreg *muxregs, u8 count, bool enable)
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{
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struct spear_muxreg *muxreg;
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u32 val, temp, j;
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for (j = 0; j < count; j++) {
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muxreg = &muxregs[j];
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val = pmx_readl(pmx, muxreg->reg);
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val &= ~muxreg->mask;
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if (enable)
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temp = muxreg->val;
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else
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temp = ~muxreg->val;
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val |= muxreg->mask & temp;
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pmx_writel(pmx, val, muxreg->reg);
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}
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}
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static int set_mode(struct spear_pmx *pmx, int mode)
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{
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struct spear_pmx_mode *pmx_mode = NULL;
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int i;
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u32 val;
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if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes)
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return -EINVAL;
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for (i = 0; i < pmx->machdata->npmx_modes; i++) {
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if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) {
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pmx_mode = pmx->machdata->pmx_modes[i];
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break;
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}
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}
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if (!pmx_mode)
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return -EINVAL;
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val = pmx_readl(pmx, pmx_mode->reg);
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val &= ~pmx_mode->mask;
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val |= pmx_mode->val;
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pmx_writel(pmx, val, pmx_mode->reg);
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pmx->machdata->mode = pmx_mode->mode;
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dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n",
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pmx_mode->name ? pmx_mode->name : "no_name",
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pmx_mode->reg);
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return 0;
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}
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void pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
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unsigned count, u16 reg)
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{
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int i, j;
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for (i = 0; i < count; i++)
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for (j = 0; j < gpio_pingroup[i].nmuxregs; j++)
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gpio_pingroup[i].muxregs[j].reg = reg;
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}
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void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)
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{
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struct spear_pingroup *pgroup;
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struct spear_modemux *modemux;
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int i, j, group;
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for (group = 0; group < machdata->ngroups; group++) {
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pgroup = machdata->groups[group];
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for (i = 0; i < pgroup->nmodemuxs; i++) {
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modemux = &pgroup->modemuxs[i];
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for (j = 0; j < modemux->nmuxregs; j++)
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if (modemux->muxregs[j].reg == 0xFFFF)
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modemux->muxregs[j].reg = reg;
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}
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}
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}
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static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev)
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{
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struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->machdata->ngroups;
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}
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static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
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unsigned group)
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{
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struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->machdata->groups[group]->name;
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}
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static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned group, const unsigned **pins, unsigned *num_pins)
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{
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struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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*pins = pmx->machdata->groups[group]->pins;
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*num_pins = pmx->machdata->groups[group]->npins;
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return 0;
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}
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static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s, unsigned offset)
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{
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seq_printf(s, " " DRIVER_NAME);
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}
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static int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *np_config,
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struct pinctrl_map **map,
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unsigned *num_maps)
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{
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struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct device_node *np;
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struct property *prop;
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const char *function, *group;
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int ret, index = 0, count = 0;
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/* calculate number of maps required */
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for_each_child_of_node(np_config, np) {
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ret = of_property_read_string(np, "st,function", &function);
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if (ret < 0)
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return ret;
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ret = of_property_count_strings(np, "st,pins");
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if (ret < 0)
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return ret;
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count += ret;
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}
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if (!count) {
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dev_err(pmx->dev, "No child nodes passed via DT\n");
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return -ENODEV;
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}
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*map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
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if (!*map)
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return -ENOMEM;
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for_each_child_of_node(np_config, np) {
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of_property_read_string(np, "st,function", &function);
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of_property_for_each_string(np, "st,pins", prop, group) {
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(*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
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(*map)[index].data.mux.group = group;
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(*map)[index].data.mux.function = function;
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index++;
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}
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}
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*num_maps = count;
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return 0;
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}
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static void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
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struct pinctrl_map *map,
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unsigned num_maps)
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{
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kfree(map);
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}
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static const struct pinctrl_ops spear_pinctrl_ops = {
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.get_groups_count = spear_pinctrl_get_groups_cnt,
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.get_group_name = spear_pinctrl_get_group_name,
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.get_group_pins = spear_pinctrl_get_group_pins,
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.pin_dbg_show = spear_pinctrl_pin_dbg_show,
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.dt_node_to_map = spear_pinctrl_dt_node_to_map,
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.dt_free_map = spear_pinctrl_dt_free_map,
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};
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static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
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{
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struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->machdata->nfunctions;
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}
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static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
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unsigned function)
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{
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struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->machdata->functions[function]->name;
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}
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static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
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unsigned function, const char *const **groups,
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unsigned * const ngroups)
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{
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struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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*groups = pmx->machdata->functions[function]->groups;
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*ngroups = pmx->machdata->functions[function]->ngroups;
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return 0;
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}
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static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
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unsigned function, unsigned group, bool enable)
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{
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struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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const struct spear_pingroup *pgroup;
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const struct spear_modemux *modemux;
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int i;
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bool found = false;
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pgroup = pmx->machdata->groups[group];
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for (i = 0; i < pgroup->nmodemuxs; i++) {
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modemux = &pgroup->modemuxs[i];
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/* SoC have any modes */
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if (pmx->machdata->modes_supported) {
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if (!(pmx->machdata->mode & modemux->modes))
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continue;
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}
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found = true;
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muxregs_endisable(pmx, modemux->muxregs, modemux->nmuxregs,
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enable);
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}
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if (!found) {
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dev_err(pmx->dev, "pinmux group: %s not supported\n",
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pgroup->name);
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return -ENODEV;
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}
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return 0;
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}
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static int spear_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned function,
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unsigned group)
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{
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return spear_pinctrl_endisable(pctldev, function, group, true);
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}
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/* gpio with pinmux */
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static struct spear_gpio_pingroup *get_gpio_pingroup(struct spear_pmx *pmx,
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unsigned pin)
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{
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struct spear_gpio_pingroup *gpio_pingroup;
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int i, j;
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if (!pmx->machdata->gpio_pingroups)
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return NULL;
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for (i = 0; i < pmx->machdata->ngpio_pingroups; i++) {
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gpio_pingroup = &pmx->machdata->gpio_pingroups[i];
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for (j = 0; j < gpio_pingroup->npins; j++) {
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if (gpio_pingroup->pins[j] == pin)
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return gpio_pingroup;
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}
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}
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return NULL;
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}
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static int gpio_request_endisable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range, unsigned offset, bool enable)
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{
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struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct spear_pinctrl_machdata *machdata = pmx->machdata;
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struct spear_gpio_pingroup *gpio_pingroup;
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/*
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* Some SoC have configuration options applicable to group of pins,
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* rather than a single pin.
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*/
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gpio_pingroup = get_gpio_pingroup(pmx, offset);
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if (gpio_pingroup)
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muxregs_endisable(pmx, gpio_pingroup->muxregs,
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gpio_pingroup->nmuxregs, enable);
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/*
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* SoC may need some extra configurations, or configurations for single
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* pin
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*/
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if (machdata->gpio_request_endisable)
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machdata->gpio_request_endisable(pmx, offset, enable);
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return 0;
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}
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static int gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range, unsigned offset)
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{
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return gpio_request_endisable(pctldev, range, offset, true);
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}
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static void gpio_disable_free(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range, unsigned offset)
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{
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gpio_request_endisable(pctldev, range, offset, false);
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}
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static const struct pinmux_ops spear_pinmux_ops = {
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.get_functions_count = spear_pinctrl_get_funcs_count,
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.get_function_name = spear_pinctrl_get_func_name,
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.get_function_groups = spear_pinctrl_get_func_groups,
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.set_mux = spear_pinctrl_set_mux,
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.gpio_request_enable = gpio_request_enable,
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.gpio_disable_free = gpio_disable_free,
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};
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static struct pinctrl_desc spear_pinctrl_desc = {
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.name = DRIVER_NAME,
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.pctlops = &spear_pinctrl_ops,
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.pmxops = &spear_pinmux_ops,
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.owner = THIS_MODULE,
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};
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int spear_pinctrl_probe(struct platform_device *pdev,
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struct spear_pinctrl_machdata *machdata)
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{
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struct device_node *np = pdev->dev.of_node;
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struct resource *res;
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struct spear_pmx *pmx;
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if (!machdata)
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return -ENODEV;
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pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
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if (!pmx) {
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dev_err(&pdev->dev, "Can't alloc spear_pmx\n");
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return -ENOMEM;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pmx->vbase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pmx->vbase))
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return PTR_ERR(pmx->vbase);
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pmx->dev = &pdev->dev;
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pmx->machdata = machdata;
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/* configure mode, if supported by SoC */
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if (machdata->modes_supported) {
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int mode = 0;
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if (of_property_read_u32(np, "st,pinmux-mode", &mode)) {
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dev_err(&pdev->dev, "OF: pinmux mode not passed\n");
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return -EINVAL;
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}
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if (set_mode(pmx, mode)) {
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dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n",
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mode);
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return -EINVAL;
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}
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}
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platform_set_drvdata(pdev, pmx);
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spear_pinctrl_desc.pins = machdata->pins;
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spear_pinctrl_desc.npins = machdata->npins;
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pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx);
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if (IS_ERR(pmx->pctl)) {
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dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
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return PTR_ERR(pmx->pctl);
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}
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return 0;
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}
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int spear_pinctrl_remove(struct platform_device *pdev)
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{
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struct spear_pmx *pmx = platform_get_drvdata(pdev);
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pinctrl_unregister(pmx->pctl);
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return 0;
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}
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