476 lines
15 KiB
C
476 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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* Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
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*/
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#include <linux/mdio.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/of.h>
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#include <linux/bitfield.h>
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#define XWAY_MDIO_MIICTRL 0x17 /* mii control */
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#define XWAY_MDIO_IMASK 0x19 /* interrupt mask */
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#define XWAY_MDIO_ISTAT 0x1A /* interrupt status */
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#define XWAY_MDIO_LED 0x1B /* led control */
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#define XWAY_MDIO_MIICTRL_RXSKEW_MASK GENMASK(14, 12)
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#define XWAY_MDIO_MIICTRL_TXSKEW_MASK GENMASK(10, 8)
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/* bit 15:12 are reserved */
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#define XWAY_MDIO_LED_LED3_EN BIT(11) /* Enable the integrated function of LED3 */
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#define XWAY_MDIO_LED_LED2_EN BIT(10) /* Enable the integrated function of LED2 */
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#define XWAY_MDIO_LED_LED1_EN BIT(9) /* Enable the integrated function of LED1 */
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#define XWAY_MDIO_LED_LED0_EN BIT(8) /* Enable the integrated function of LED0 */
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/* bit 7:4 are reserved */
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#define XWAY_MDIO_LED_LED3_DA BIT(3) /* Direct Access to LED3 */
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#define XWAY_MDIO_LED_LED2_DA BIT(2) /* Direct Access to LED2 */
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#define XWAY_MDIO_LED_LED1_DA BIT(1) /* Direct Access to LED1 */
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#define XWAY_MDIO_LED_LED0_DA BIT(0) /* Direct Access to LED0 */
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#define XWAY_MDIO_INIT_WOL BIT(15) /* Wake-On-LAN */
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#define XWAY_MDIO_INIT_MSRE BIT(14)
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#define XWAY_MDIO_INIT_NPRX BIT(13)
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#define XWAY_MDIO_INIT_NPTX BIT(12)
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#define XWAY_MDIO_INIT_ANE BIT(11) /* Auto-Neg error */
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#define XWAY_MDIO_INIT_ANC BIT(10) /* Auto-Neg complete */
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#define XWAY_MDIO_INIT_ADSC BIT(5) /* Link auto-downspeed detect */
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#define XWAY_MDIO_INIT_MPIPC BIT(4)
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#define XWAY_MDIO_INIT_MDIXC BIT(3)
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#define XWAY_MDIO_INIT_DXMC BIT(2) /* Duplex mode change */
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#define XWAY_MDIO_INIT_LSPC BIT(1) /* Link speed change */
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#define XWAY_MDIO_INIT_LSTC BIT(0) /* Link state change */
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#define XWAY_MDIO_INIT_MASK (XWAY_MDIO_INIT_LSTC | \
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XWAY_MDIO_INIT_ADSC)
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#define ADVERTISED_MPD BIT(10) /* Multi-port device */
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/* LED Configuration */
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#define XWAY_MMD_LEDCH 0x01E0
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/* Inverse of SCAN Function */
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#define XWAY_MMD_LEDCH_NACS_NONE 0x0000
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#define XWAY_MMD_LEDCH_NACS_LINK 0x0001
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#define XWAY_MMD_LEDCH_NACS_PDOWN 0x0002
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#define XWAY_MMD_LEDCH_NACS_EEE 0x0003
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#define XWAY_MMD_LEDCH_NACS_ANEG 0x0004
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#define XWAY_MMD_LEDCH_NACS_ABIST 0x0005
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#define XWAY_MMD_LEDCH_NACS_CDIAG 0x0006
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#define XWAY_MMD_LEDCH_NACS_TEST 0x0007
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/* Slow Blink Frequency */
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#define XWAY_MMD_LEDCH_SBF_F02HZ 0x0000
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#define XWAY_MMD_LEDCH_SBF_F04HZ 0x0010
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#define XWAY_MMD_LEDCH_SBF_F08HZ 0x0020
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#define XWAY_MMD_LEDCH_SBF_F16HZ 0x0030
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/* Fast Blink Frequency */
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#define XWAY_MMD_LEDCH_FBF_F02HZ 0x0000
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#define XWAY_MMD_LEDCH_FBF_F04HZ 0x0040
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#define XWAY_MMD_LEDCH_FBF_F08HZ 0x0080
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#define XWAY_MMD_LEDCH_FBF_F16HZ 0x00C0
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/* LED Configuration */
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#define XWAY_MMD_LEDCL 0x01E1
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/* Complex Blinking Configuration */
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#define XWAY_MMD_LEDCH_CBLINK_NONE 0x0000
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#define XWAY_MMD_LEDCH_CBLINK_LINK 0x0001
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#define XWAY_MMD_LEDCH_CBLINK_PDOWN 0x0002
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#define XWAY_MMD_LEDCH_CBLINK_EEE 0x0003
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#define XWAY_MMD_LEDCH_CBLINK_ANEG 0x0004
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#define XWAY_MMD_LEDCH_CBLINK_ABIST 0x0005
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#define XWAY_MMD_LEDCH_CBLINK_CDIAG 0x0006
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#define XWAY_MMD_LEDCH_CBLINK_TEST 0x0007
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/* Complex SCAN Configuration */
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#define XWAY_MMD_LEDCH_SCAN_NONE 0x0000
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#define XWAY_MMD_LEDCH_SCAN_LINK 0x0010
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#define XWAY_MMD_LEDCH_SCAN_PDOWN 0x0020
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#define XWAY_MMD_LEDCH_SCAN_EEE 0x0030
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#define XWAY_MMD_LEDCH_SCAN_ANEG 0x0040
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#define XWAY_MMD_LEDCH_SCAN_ABIST 0x0050
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#define XWAY_MMD_LEDCH_SCAN_CDIAG 0x0060
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#define XWAY_MMD_LEDCH_SCAN_TEST 0x0070
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/* Configuration for LED Pin x */
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#define XWAY_MMD_LED0H 0x01E2
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/* Fast Blinking Configuration */
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#define XWAY_MMD_LEDxH_BLINKF_MASK 0x000F
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#define XWAY_MMD_LEDxH_BLINKF_NONE 0x0000
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#define XWAY_MMD_LEDxH_BLINKF_LINK10 0x0001
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#define XWAY_MMD_LEDxH_BLINKF_LINK100 0x0002
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#define XWAY_MMD_LEDxH_BLINKF_LINK10X 0x0003
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#define XWAY_MMD_LEDxH_BLINKF_LINK1000 0x0004
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#define XWAY_MMD_LEDxH_BLINKF_LINK10_0 0x0005
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#define XWAY_MMD_LEDxH_BLINKF_LINK100X 0x0006
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#define XWAY_MMD_LEDxH_BLINKF_LINK10XX 0x0007
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#define XWAY_MMD_LEDxH_BLINKF_PDOWN 0x0008
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#define XWAY_MMD_LEDxH_BLINKF_EEE 0x0009
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#define XWAY_MMD_LEDxH_BLINKF_ANEG 0x000A
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#define XWAY_MMD_LEDxH_BLINKF_ABIST 0x000B
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#define XWAY_MMD_LEDxH_BLINKF_CDIAG 0x000C
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/* Constant On Configuration */
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#define XWAY_MMD_LEDxH_CON_MASK 0x00F0
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#define XWAY_MMD_LEDxH_CON_NONE 0x0000
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#define XWAY_MMD_LEDxH_CON_LINK10 0x0010
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#define XWAY_MMD_LEDxH_CON_LINK100 0x0020
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#define XWAY_MMD_LEDxH_CON_LINK10X 0x0030
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#define XWAY_MMD_LEDxH_CON_LINK1000 0x0040
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#define XWAY_MMD_LEDxH_CON_LINK10_0 0x0050
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#define XWAY_MMD_LEDxH_CON_LINK100X 0x0060
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#define XWAY_MMD_LEDxH_CON_LINK10XX 0x0070
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#define XWAY_MMD_LEDxH_CON_PDOWN 0x0080
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#define XWAY_MMD_LEDxH_CON_EEE 0x0090
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#define XWAY_MMD_LEDxH_CON_ANEG 0x00A0
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#define XWAY_MMD_LEDxH_CON_ABIST 0x00B0
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#define XWAY_MMD_LEDxH_CON_CDIAG 0x00C0
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#define XWAY_MMD_LEDxH_CON_COPPER 0x00D0
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#define XWAY_MMD_LEDxH_CON_FIBER 0x00E0
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/* Configuration for LED Pin x */
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#define XWAY_MMD_LED0L 0x01E3
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/* Pulsing Configuration */
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#define XWAY_MMD_LEDxL_PULSE_MASK 0x000F
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#define XWAY_MMD_LEDxL_PULSE_NONE 0x0000
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#define XWAY_MMD_LEDxL_PULSE_TXACT 0x0001
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#define XWAY_MMD_LEDxL_PULSE_RXACT 0x0002
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#define XWAY_MMD_LEDxL_PULSE_COL 0x0004
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/* Slow Blinking Configuration */
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#define XWAY_MMD_LEDxL_BLINKS_MASK 0x00F0
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#define XWAY_MMD_LEDxL_BLINKS_NONE 0x0000
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#define XWAY_MMD_LEDxL_BLINKS_LINK10 0x0010
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#define XWAY_MMD_LEDxL_BLINKS_LINK100 0x0020
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#define XWAY_MMD_LEDxL_BLINKS_LINK10X 0x0030
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#define XWAY_MMD_LEDxL_BLINKS_LINK1000 0x0040
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#define XWAY_MMD_LEDxL_BLINKS_LINK10_0 0x0050
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#define XWAY_MMD_LEDxL_BLINKS_LINK100X 0x0060
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#define XWAY_MMD_LEDxL_BLINKS_LINK10XX 0x0070
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#define XWAY_MMD_LEDxL_BLINKS_PDOWN 0x0080
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#define XWAY_MMD_LEDxL_BLINKS_EEE 0x0090
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#define XWAY_MMD_LEDxL_BLINKS_ANEG 0x00A0
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#define XWAY_MMD_LEDxL_BLINKS_ABIST 0x00B0
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#define XWAY_MMD_LEDxL_BLINKS_CDIAG 0x00C0
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#define XWAY_MMD_LED1H 0x01E4
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#define XWAY_MMD_LED1L 0x01E5
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#define XWAY_MMD_LED2H 0x01E6
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#define XWAY_MMD_LED2L 0x01E7
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#define XWAY_MMD_LED3H 0x01E8
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#define XWAY_MMD_LED3L 0x01E9
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#define PHY_ID_PHY11G_1_3 0x030260D1
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#define PHY_ID_PHY22F_1_3 0x030260E1
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#define PHY_ID_PHY11G_1_4 0xD565A400
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#define PHY_ID_PHY22F_1_4 0xD565A410
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#define PHY_ID_PHY11G_1_5 0xD565A401
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#define PHY_ID_PHY22F_1_5 0xD565A411
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#define PHY_ID_PHY11G_VR9_1_1 0xD565A408
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#define PHY_ID_PHY22F_VR9_1_1 0xD565A418
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#define PHY_ID_PHY11G_VR9_1_2 0xD565A409
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#define PHY_ID_PHY22F_VR9_1_2 0xD565A419
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static const int xway_internal_delay[] = {0, 500, 1000, 1500, 2000, 2500,
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3000, 3500};
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static int xway_gphy_rgmii_init(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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unsigned int delay_size = ARRAY_SIZE(xway_internal_delay);
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s32 int_delay;
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int val = 0;
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if (!phy_interface_is_rgmii(phydev))
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return 0;
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/* Existing behavior was to use default pin strapping delay in rgmii
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* mode, but rgmii should have meant no delay. Warn existing users,
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* but do not change anything at the moment.
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*/
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
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u16 txskew, rxskew;
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val = phy_read(phydev, XWAY_MDIO_MIICTRL);
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if (val < 0)
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return val;
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txskew = FIELD_GET(XWAY_MDIO_MIICTRL_TXSKEW_MASK, val);
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rxskew = FIELD_GET(XWAY_MDIO_MIICTRL_RXSKEW_MASK, val);
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if (txskew > 0 || rxskew > 0)
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phydev_warn(phydev,
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"PHY has delays (e.g. via pin strapping), but phy-mode = 'rgmii'\n"
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"Should be 'rgmii-id' to use internal delays txskew:%d ps rxskew:%d ps\n",
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xway_internal_delay[txskew],
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xway_internal_delay[rxskew]);
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return 0;
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}
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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int_delay = phy_get_internal_delay(phydev, dev,
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xway_internal_delay,
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delay_size, true);
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/* if rx-internal-delay-ps is missing, use default of 2.0 ns */
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if (int_delay < 0)
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int_delay = 4; /* 2000 ps */
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val |= FIELD_PREP(XWAY_MDIO_MIICTRL_RXSKEW_MASK, int_delay);
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}
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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int_delay = phy_get_internal_delay(phydev, dev,
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xway_internal_delay,
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delay_size, false);
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/* if tx-internal-delay-ps is missing, use default of 2.0 ns */
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if (int_delay < 0)
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int_delay = 4; /* 2000 ps */
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val |= FIELD_PREP(XWAY_MDIO_MIICTRL_TXSKEW_MASK, int_delay);
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}
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return phy_modify(phydev, XWAY_MDIO_MIICTRL,
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XWAY_MDIO_MIICTRL_RXSKEW_MASK |
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XWAY_MDIO_MIICTRL_TXSKEW_MASK, val);
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}
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static int xway_gphy_config_init(struct phy_device *phydev)
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{
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int err;
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u32 ledxh;
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u32 ledxl;
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/* Mask all interrupts */
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err = phy_write(phydev, XWAY_MDIO_IMASK, 0);
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if (err)
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return err;
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/* Clear all pending interrupts */
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phy_read(phydev, XWAY_MDIO_ISTAT);
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/* Ensure that integrated led function is enabled for all leds */
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err = phy_write(phydev, XWAY_MDIO_LED,
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XWAY_MDIO_LED_LED0_EN |
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XWAY_MDIO_LED_LED1_EN |
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XWAY_MDIO_LED_LED2_EN |
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XWAY_MDIO_LED_LED3_EN);
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if (err)
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return err;
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phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH,
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XWAY_MMD_LEDCH_NACS_NONE |
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XWAY_MMD_LEDCH_SBF_F02HZ |
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XWAY_MMD_LEDCH_FBF_F16HZ);
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phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL,
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XWAY_MMD_LEDCH_CBLINK_NONE |
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XWAY_MMD_LEDCH_SCAN_NONE);
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/**
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* In most cases only one LED is connected to this phy, so
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* configure them all to constant on and pulse mode. LED3 is
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* only available in some packages, leave it in its reset
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* configuration.
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*/
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ledxh = XWAY_MMD_LEDxH_BLINKF_NONE | XWAY_MMD_LEDxH_CON_LINK10XX;
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ledxl = XWAY_MMD_LEDxL_PULSE_TXACT | XWAY_MMD_LEDxL_PULSE_RXACT |
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XWAY_MMD_LEDxL_BLINKS_NONE;
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phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh);
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phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl);
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phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh);
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phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl);
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phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh);
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phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl);
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err = xway_gphy_rgmii_init(phydev);
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if (err)
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return err;
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return 0;
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}
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static int xway_gphy14_config_aneg(struct phy_device *phydev)
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{
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int reg, err;
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/* Advertise as multi-port device, see IEEE802.3-2002 40.5.1.1 */
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/* This is a workaround for an errata in rev < 1.5 devices */
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reg = phy_read(phydev, MII_CTRL1000);
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reg |= ADVERTISED_MPD;
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err = phy_write(phydev, MII_CTRL1000, reg);
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if (err)
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return err;
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return genphy_config_aneg(phydev);
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}
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static int xway_gphy_ack_interrupt(struct phy_device *phydev)
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{
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int reg;
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reg = phy_read(phydev, XWAY_MDIO_ISTAT);
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return (reg < 0) ? reg : 0;
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}
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static int xway_gphy_config_intr(struct phy_device *phydev)
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{
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u16 mask = 0;
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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err = xway_gphy_ack_interrupt(phydev);
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if (err)
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return err;
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mask = XWAY_MDIO_INIT_MASK;
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err = phy_write(phydev, XWAY_MDIO_IMASK, mask);
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} else {
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err = phy_write(phydev, XWAY_MDIO_IMASK, mask);
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if (err)
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return err;
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err = xway_gphy_ack_interrupt(phydev);
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}
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return err;
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}
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static irqreturn_t xway_gphy_handle_interrupt(struct phy_device *phydev)
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{
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int irq_status;
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irq_status = phy_read(phydev, XWAY_MDIO_ISTAT);
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if (irq_status < 0) {
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phy_error(phydev);
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return IRQ_NONE;
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}
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if (!(irq_status & XWAY_MDIO_INIT_MASK))
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return IRQ_NONE;
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phy_trigger_machine(phydev);
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return IRQ_HANDLED;
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}
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static struct phy_driver xway_gphy[] = {
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{
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.phy_id = PHY_ID_PHY11G_1_3,
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.phy_id_mask = 0xffffffff,
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.name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.3",
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/* PHY_GBIT_FEATURES */
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.config_init = xway_gphy_config_init,
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.config_aneg = xway_gphy14_config_aneg,
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.handle_interrupt = xway_gphy_handle_interrupt,
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.config_intr = xway_gphy_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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.phy_id = PHY_ID_PHY22F_1_3,
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.phy_id_mask = 0xffffffff,
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.name = "Intel XWAY PHY22F (PEF 7061) v1.3",
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/* PHY_BASIC_FEATURES */
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.config_init = xway_gphy_config_init,
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.config_aneg = xway_gphy14_config_aneg,
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.handle_interrupt = xway_gphy_handle_interrupt,
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.config_intr = xway_gphy_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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.phy_id = PHY_ID_PHY11G_1_4,
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.phy_id_mask = 0xffffffff,
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.name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.4",
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/* PHY_GBIT_FEATURES */
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.config_init = xway_gphy_config_init,
|
|
.config_aneg = xway_gphy14_config_aneg,
|
|
.handle_interrupt = xway_gphy_handle_interrupt,
|
|
.config_intr = xway_gphy_config_intr,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_PHY22F_1_4,
|
|
.phy_id_mask = 0xffffffff,
|
|
.name = "Intel XWAY PHY22F (PEF 7061) v1.4",
|
|
/* PHY_BASIC_FEATURES */
|
|
.config_init = xway_gphy_config_init,
|
|
.config_aneg = xway_gphy14_config_aneg,
|
|
.handle_interrupt = xway_gphy_handle_interrupt,
|
|
.config_intr = xway_gphy_config_intr,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_PHY11G_1_5,
|
|
.phy_id_mask = 0xffffffff,
|
|
.name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.5 / v1.6",
|
|
/* PHY_GBIT_FEATURES */
|
|
.config_init = xway_gphy_config_init,
|
|
.handle_interrupt = xway_gphy_handle_interrupt,
|
|
.config_intr = xway_gphy_config_intr,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_PHY22F_1_5,
|
|
.phy_id_mask = 0xffffffff,
|
|
.name = "Intel XWAY PHY22F (PEF 7061) v1.5 / v1.6",
|
|
/* PHY_BASIC_FEATURES */
|
|
.config_init = xway_gphy_config_init,
|
|
.handle_interrupt = xway_gphy_handle_interrupt,
|
|
.config_intr = xway_gphy_config_intr,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_PHY11G_VR9_1_1,
|
|
.phy_id_mask = 0xffffffff,
|
|
.name = "Intel XWAY PHY11G (xRX v1.1 integrated)",
|
|
/* PHY_GBIT_FEATURES */
|
|
.config_init = xway_gphy_config_init,
|
|
.handle_interrupt = xway_gphy_handle_interrupt,
|
|
.config_intr = xway_gphy_config_intr,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_PHY22F_VR9_1_1,
|
|
.phy_id_mask = 0xffffffff,
|
|
.name = "Intel XWAY PHY22F (xRX v1.1 integrated)",
|
|
/* PHY_BASIC_FEATURES */
|
|
.config_init = xway_gphy_config_init,
|
|
.handle_interrupt = xway_gphy_handle_interrupt,
|
|
.config_intr = xway_gphy_config_intr,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_PHY11G_VR9_1_2,
|
|
.phy_id_mask = 0xffffffff,
|
|
.name = "Intel XWAY PHY11G (xRX v1.2 integrated)",
|
|
/* PHY_GBIT_FEATURES */
|
|
.config_init = xway_gphy_config_init,
|
|
.handle_interrupt = xway_gphy_handle_interrupt,
|
|
.config_intr = xway_gphy_config_intr,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_PHY22F_VR9_1_2,
|
|
.phy_id_mask = 0xffffffff,
|
|
.name = "Intel XWAY PHY22F (xRX v1.2 integrated)",
|
|
/* PHY_BASIC_FEATURES */
|
|
.config_init = xway_gphy_config_init,
|
|
.handle_interrupt = xway_gphy_handle_interrupt,
|
|
.config_intr = xway_gphy_config_intr,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
},
|
|
};
|
|
module_phy_driver(xway_gphy);
|
|
|
|
static struct mdio_device_id __maybe_unused xway_gphy_tbl[] = {
|
|
{ PHY_ID_PHY11G_1_3, 0xffffffff },
|
|
{ PHY_ID_PHY22F_1_3, 0xffffffff },
|
|
{ PHY_ID_PHY11G_1_4, 0xffffffff },
|
|
{ PHY_ID_PHY22F_1_4, 0xffffffff },
|
|
{ PHY_ID_PHY11G_1_5, 0xffffffff },
|
|
{ PHY_ID_PHY22F_1_5, 0xffffffff },
|
|
{ PHY_ID_PHY11G_VR9_1_1, 0xffffffff },
|
|
{ PHY_ID_PHY22F_VR9_1_1, 0xffffffff },
|
|
{ PHY_ID_PHY11G_VR9_1_2, 0xffffffff },
|
|
{ PHY_ID_PHY22F_VR9_1_2, 0xffffffff },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(mdio, xway_gphy_tbl);
|
|
|
|
MODULE_DESCRIPTION("Intel XWAY PHY driver");
|
|
MODULE_LICENSE("GPL");
|