186 lines
5.4 KiB
C
186 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright 2021 NXP
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*/
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#include <linux/pcs/pcs-xpcs.h>
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#include "pcs-xpcs.h"
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/* LANE_DRIVER1_0 register */
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#define SJA1110_LANE_DRIVER1_0 0x8038
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#define SJA1110_TXDRV(x) (((x) << 12) & GENMASK(14, 12))
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/* LANE_DRIVER2_0 register */
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#define SJA1110_LANE_DRIVER2_0 0x803a
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#define SJA1110_TXDRVTRIM_LSB(x) ((x) & GENMASK_ULL(15, 0))
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/* LANE_DRIVER2_1 register */
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#define SJA1110_LANE_DRIVER2_1 0x803b
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#define SJA1110_LANE_DRIVER2_1_RSV BIT(9)
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#define SJA1110_TXDRVTRIM_MSB(x) (((x) & GENMASK_ULL(23, 16)) >> 16)
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/* LANE_TRIM register */
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#define SJA1110_LANE_TRIM 0x8040
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#define SJA1110_TXTEN BIT(11)
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#define SJA1110_TXRTRIM(x) (((x) << 8) & GENMASK(10, 8))
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#define SJA1110_TXPLL_BWSEL BIT(7)
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#define SJA1110_RXTEN BIT(6)
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#define SJA1110_RXRTRIM(x) (((x) << 3) & GENMASK(5, 3))
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#define SJA1110_CDR_GAIN BIT(2)
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#define SJA1110_ACCOUPLE_RXVCM_EN BIT(0)
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/* LANE_DATAPATH_1 register */
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#define SJA1110_LANE_DATAPATH_1 0x8037
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/* POWERDOWN_ENABLE register */
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#define SJA1110_POWERDOWN_ENABLE 0x8041
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#define SJA1110_TXPLL_PD BIT(12)
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#define SJA1110_TXPD BIT(11)
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#define SJA1110_RXPKDETEN BIT(10)
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#define SJA1110_RXCH_PD BIT(9)
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#define SJA1110_RXBIAS_PD BIT(8)
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#define SJA1110_RESET_SER_EN BIT(7)
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#define SJA1110_RESET_SER BIT(6)
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#define SJA1110_RESET_DES BIT(5)
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#define SJA1110_RCVEN BIT(4)
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/* RXPLL_CTRL0 register */
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#define SJA1110_RXPLL_CTRL0 0x8065
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#define SJA1110_RXPLL_FBDIV(x) (((x) << 2) & GENMASK(9, 2))
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/* RXPLL_CTRL1 register */
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#define SJA1110_RXPLL_CTRL1 0x8066
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#define SJA1110_RXPLL_REFDIV(x) ((x) & GENMASK(4, 0))
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/* TXPLL_CTRL0 register */
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#define SJA1110_TXPLL_CTRL0 0x806d
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#define SJA1110_TXPLL_FBDIV(x) ((x) & GENMASK(11, 0))
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/* TXPLL_CTRL1 register */
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#define SJA1110_TXPLL_CTRL1 0x806e
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#define SJA1110_TXPLL_REFDIV(x) ((x) & GENMASK(5, 0))
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/* RX_DATA_DETECT register */
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#define SJA1110_RX_DATA_DETECT 0x8045
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/* RX_CDR_CTLE register */
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#define SJA1110_RX_CDR_CTLE 0x8042
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/* In NXP SJA1105, the PCS is integrated with a PMA that has the TX lane
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* polarity inverted by default (PLUS is MINUS, MINUS is PLUS). To obtain
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* normal non-inverted behavior, the TX lane polarity must be inverted in the
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* PCS, via the DIGITAL_CONTROL_2 register.
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*/
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int nxp_sja1105_sgmii_pma_config(struct dw_xpcs *xpcs)
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{
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return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL2,
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DW_VR_MII_DIG_CTRL2_TX_POL_INV);
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}
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static int nxp_sja1110_pma_config(struct dw_xpcs *xpcs,
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u16 txpll_fbdiv, u16 txpll_refdiv,
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u16 rxpll_fbdiv, u16 rxpll_refdiv,
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u16 rx_cdr_ctle)
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{
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u16 val;
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int ret;
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/* Program TX PLL feedback divider and reference divider settings for
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* correct oscillation frequency.
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*/
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL0,
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SJA1110_TXPLL_FBDIV(txpll_fbdiv));
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if (ret < 0)
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return ret;
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL1,
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SJA1110_TXPLL_REFDIV(txpll_refdiv));
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if (ret < 0)
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return ret;
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/* Program transmitter amplitude and disable amplitude trimming */
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER1_0,
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SJA1110_TXDRV(0x5));
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if (ret < 0)
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return ret;
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val = SJA1110_TXDRVTRIM_LSB(0xffffffull);
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER2_0, val);
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if (ret < 0)
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return ret;
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val = SJA1110_TXDRVTRIM_MSB(0xffffffull) | SJA1110_LANE_DRIVER2_1_RSV;
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER2_1, val);
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if (ret < 0)
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return ret;
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/* Enable input and output resistor terminations for low BER. */
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val = SJA1110_ACCOUPLE_RXVCM_EN | SJA1110_CDR_GAIN |
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SJA1110_RXRTRIM(4) | SJA1110_RXTEN | SJA1110_TXPLL_BWSEL |
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SJA1110_TXRTRIM(3) | SJA1110_TXTEN;
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_TRIM, val);
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if (ret < 0)
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return ret;
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/* Select PCS as transmitter data source. */
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DATAPATH_1, 0);
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if (ret < 0)
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return ret;
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/* Program RX PLL feedback divider and reference divider for correct
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* oscillation frequency.
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*/
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL0,
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SJA1110_RXPLL_FBDIV(rxpll_fbdiv));
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if (ret < 0)
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return ret;
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL1,
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SJA1110_RXPLL_REFDIV(rxpll_refdiv));
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if (ret < 0)
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return ret;
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/* Program threshold for receiver signal detector.
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* Enable control of RXPLL by receiver signal detector to disable RXPLL
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* when an input signal is not present.
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*/
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RX_DATA_DETECT, 0x0005);
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if (ret < 0)
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return ret;
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/* Enable TX and RX PLLs and circuits.
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* Release reset of PMA to enable data flow to/from PCS.
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*/
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ret = xpcs_read(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE);
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if (ret < 0)
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return ret;
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val = ret & ~(SJA1110_TXPLL_PD | SJA1110_TXPD | SJA1110_RXCH_PD |
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SJA1110_RXBIAS_PD | SJA1110_RESET_SER_EN |
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SJA1110_RESET_SER | SJA1110_RESET_DES);
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val |= SJA1110_RXPKDETEN | SJA1110_RCVEN;
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE, val);
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if (ret < 0)
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return ret;
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/* Program continuous-time linear equalizer (CTLE) settings. */
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RX_CDR_CTLE,
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rx_cdr_ctle);
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if (ret < 0)
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return ret;
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return 0;
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}
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int nxp_sja1110_sgmii_pma_config(struct dw_xpcs *xpcs)
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{
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return nxp_sja1110_pma_config(xpcs, 0x19, 0x1, 0x19, 0x1, 0x212a);
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}
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int nxp_sja1110_2500basex_pma_config(struct dw_xpcs *xpcs)
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{
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return nxp_sja1110_pma_config(xpcs, 0x7d, 0x2, 0x7d, 0x2, 0x732a);
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}
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