225 lines
4.4 KiB
C
225 lines
4.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012-2013 Cavium Inc., All Rights Reserved.
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*
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* MD5/SHA1/SHA256/SHA512 instruction definitions added by
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* Aaro Koskinen <aaro.koskinen@iki.fi>.
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*
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*/
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#ifndef __LINUX_OCTEON_CRYPTO_H
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#define __LINUX_OCTEON_CRYPTO_H
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#include <linux/sched.h>
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#include <asm/mipsregs.h>
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#define OCTEON_CR_OPCODE_PRIORITY 300
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extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
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extern void octeon_crypto_disable(struct octeon_cop2_state *state,
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unsigned long flags);
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/*
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* Macros needed to implement MD5/SHA1/SHA256:
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*/
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/*
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* The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256).
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*/
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#define write_octeon_64bit_hash_dword(value, index) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x0048+" STR(index) \
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: \
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: [rt] "d" (cpu_to_be64(value))); \
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} while (0)
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/*
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* The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256).
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*/
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#define read_octeon_64bit_hash_dword(index) \
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({ \
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u64 __value; \
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\
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__asm__ __volatile__ ( \
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"dmfc2 %[rt],0x0048+" STR(index) \
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: [rt] "=d" (__value) \
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: ); \
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\
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be64_to_cpu(__value); \
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})
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/*
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* The index can be 0-6.
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*/
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#define write_octeon_64bit_block_dword(value, index) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x0040+" STR(index) \
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: \
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: [rt] "d" (cpu_to_be64(value))); \
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} while (0)
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/*
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* The value is the final block dword (64-bit).
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*/
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#define octeon_md5_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x4047" \
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: \
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: [rt] "d" (cpu_to_be64(value))); \
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} while (0)
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/*
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* The value is the final block dword (64-bit).
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*/
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#define octeon_sha1_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x4057" \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The value is the final block dword (64-bit).
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*/
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#define octeon_sha256_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x404f" \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* Macros needed to implement SHA512:
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*/
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/*
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* The index can be 0-7.
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*/
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#define write_octeon_64bit_hash_sha512(value, index) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x0250+" STR(index) \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The index can be 0-7.
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*/
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#define read_octeon_64bit_hash_sha512(index) \
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({ \
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u64 __value; \
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\
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__asm__ __volatile__ ( \
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"dmfc2 %[rt],0x0250+" STR(index) \
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: [rt] "=d" (__value) \
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: ); \
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\
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__value; \
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})
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/*
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* The index can be 0-14.
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*/
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#define write_octeon_64bit_block_sha512(value, index) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x0240+" STR(index) \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The value is the final block word (64-bit).
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*/
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#define octeon_sha512_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x424f" \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The value is the final block dword (64-bit).
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*/
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#define octeon_sha1_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x4057" \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The value is the final block dword (64-bit).
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*/
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#define octeon_sha256_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x404f" \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* Macros needed to implement SHA512:
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*/
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/*
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* The index can be 0-7.
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*/
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#define write_octeon_64bit_hash_sha512(value, index) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x0250+" STR(index) \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The index can be 0-7.
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*/
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#define read_octeon_64bit_hash_sha512(index) \
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({ \
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u64 __value; \
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\
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__asm__ __volatile__ ( \
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"dmfc2 %[rt],0x0250+" STR(index) \
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: [rt] "=d" (__value) \
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: ); \
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\
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__value; \
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})
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/*
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* The index can be 0-14.
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*/
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#define write_octeon_64bit_block_sha512(value, index) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x0240+" STR(index) \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The value is the final block word (64-bit).
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*/
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#define octeon_sha512_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x424f" \
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: \
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: [rt] "d" (value)); \
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} while (0)
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#endif /* __LINUX_OCTEON_CRYPTO_H */
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