543 lines
13 KiB
C
543 lines
13 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König <christian.koenig@amd.com>
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*/
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#include <linux/firmware.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "r600d.h"
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/**
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* uvd_v1_0_get_rptr - get read pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring pointer
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*
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* Returns the current hardware read pointer
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*/
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uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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return RREG32(UVD_RBC_RB_RPTR);
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}
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/**
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* uvd_v1_0_get_wptr - get write pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring pointer
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*
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* Returns the current hardware write pointer
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*/
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uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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return RREG32(UVD_RBC_RB_WPTR);
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}
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/**
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* uvd_v1_0_set_wptr - set write pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring pointer
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*
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* Commits the write pointer to the hardware
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*/
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void uvd_v1_0_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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WREG32(UVD_RBC_RB_WPTR, ring->wptr);
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}
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/**
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* uvd_v1_0_fence_emit - emit an fence & trap command
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*
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* @rdev: radeon_device pointer
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* @fence: fence to emit
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*
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* Write a fence and a trap command to the ring.
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*/
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void uvd_v1_0_fence_emit(struct radeon_device *rdev,
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struct radeon_fence *fence)
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{
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struct radeon_ring *ring = &rdev->ring[fence->ring];
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uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
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radeon_ring_write(ring, addr & 0xffffffff);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
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radeon_ring_write(ring, fence->seq);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
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radeon_ring_write(ring, 2);
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return;
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}
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/**
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* uvd_v1_0_resume - memory controller programming
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*
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* @rdev: radeon_device pointer
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*
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* Let the UVD memory controller know it's offsets
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*/
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int uvd_v1_0_resume(struct radeon_device *rdev)
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{
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uint64_t addr;
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uint32_t size;
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int r;
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r = radeon_uvd_resume(rdev);
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if (r)
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return r;
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/* program the VCPU memory controller bits 0-27 */
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addr = (rdev->uvd.gpu_addr >> 3) + 16;
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size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size) >> 3;
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WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
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WREG32(UVD_VCPU_CACHE_SIZE0, size);
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addr += size;
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size = RADEON_UVD_HEAP_SIZE >> 3;
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WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
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WREG32(UVD_VCPU_CACHE_SIZE1, size);
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addr += size;
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size = (RADEON_UVD_STACK_SIZE +
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(RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;
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WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
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WREG32(UVD_VCPU_CACHE_SIZE2, size);
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/* bits 28-31 */
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addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
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WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
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/* bits 32-39 */
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addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
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WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
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WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr));
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return 0;
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}
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/**
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* uvd_v1_0_init - start and test UVD block
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*
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* @rdev: radeon_device pointer
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*
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* Initialize the hardware, boot up the VCPU and do some testing
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*/
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int uvd_v1_0_init(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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uint32_t tmp;
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int r;
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/* raise clocks while booting up the VCPU */
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if (rdev->family < CHIP_RV740)
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radeon_set_uvd_clocks(rdev, 10000, 10000);
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else
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radeon_set_uvd_clocks(rdev, 53300, 40000);
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r = uvd_v1_0_start(rdev);
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if (r)
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goto done;
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ring->ready = true;
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r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring);
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if (r) {
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ring->ready = false;
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goto done;
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}
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r = radeon_ring_lock(rdev, ring, 10);
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if (r) {
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DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r);
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goto done;
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}
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tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
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radeon_ring_write(ring, tmp);
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radeon_ring_write(ring, 0xFFFFF);
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tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
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radeon_ring_write(ring, tmp);
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radeon_ring_write(ring, 0xFFFFF);
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tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
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radeon_ring_write(ring, tmp);
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radeon_ring_write(ring, 0xFFFFF);
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/* Clear timeout status bits */
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radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));
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radeon_ring_write(ring, 0x8);
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radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));
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radeon_ring_write(ring, 3);
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radeon_ring_unlock_commit(rdev, ring, false);
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done:
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/* lower clocks again */
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radeon_set_uvd_clocks(rdev, 0, 0);
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if (!r) {
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switch (rdev->family) {
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case CHIP_RV610:
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case CHIP_RV630:
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case CHIP_RV620:
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/* 64byte granularity workaround */
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WREG32(MC_CONFIG, 0);
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WREG32(MC_CONFIG, 1 << 4);
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WREG32(RS_DQ_RD_RET_CONF, 0x3f);
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WREG32(MC_CONFIG, 0x1f);
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fallthrough;
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case CHIP_RV670:
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case CHIP_RV635:
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/* write clean workaround */
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WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10);
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break;
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default:
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/* TODO: Do we need more? */
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break;
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}
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DRM_INFO("UVD initialized successfully.\n");
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}
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return r;
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}
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/**
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* uvd_v1_0_fini - stop the hardware block
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*
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* @rdev: radeon_device pointer
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*
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* Stop the UVD block, mark ring as not ready any more
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*/
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void uvd_v1_0_fini(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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uvd_v1_0_stop(rdev);
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ring->ready = false;
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}
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/**
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* uvd_v1_0_start - start UVD block
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*
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* @rdev: radeon_device pointer
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*
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* Setup and start the UVD block
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*/
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int uvd_v1_0_start(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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uint32_t rb_bufsz;
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int i, j, r;
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/* disable byte swapping */
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u32 lmi_swap_cntl = 0;
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u32 mp_swap_cntl = 0;
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/* disable clock gating */
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WREG32(UVD_CGC_GATE, 0);
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/* disable interupt */
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WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1));
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/* Stall UMC and register bus before resetting VCPU */
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WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
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WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
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mdelay(1);
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/* put LMI, VCPU, RBC etc... into reset */
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WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |
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LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET |
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CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET);
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mdelay(5);
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/* take UVD block out of reset */
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WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD);
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mdelay(5);
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/* initialize UVD memory controller */
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WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
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(1 << 21) | (1 << 9) | (1 << 20));
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#ifdef __BIG_ENDIAN
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/* swap (8 in 32) RB and IB */
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lmi_swap_cntl = 0xa;
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mp_swap_cntl = 0;
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#endif
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WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl);
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WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl);
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WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);
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WREG32(UVD_MPC_SET_MUXA1, 0x0);
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WREG32(UVD_MPC_SET_MUXB0, 0x40c2040);
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WREG32(UVD_MPC_SET_MUXB1, 0x0);
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WREG32(UVD_MPC_SET_ALU, 0);
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WREG32(UVD_MPC_SET_MUX, 0x88);
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/* take all subblocks out of reset, except VCPU */
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WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
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mdelay(5);
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/* enable VCPU clock */
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WREG32(UVD_VCPU_CNTL, 1 << 9);
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/* enable UMC */
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WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
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WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
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/* boot up the VCPU */
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WREG32(UVD_SOFT_RESET, 0);
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mdelay(10);
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for (i = 0; i < 10; ++i) {
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uint32_t status;
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for (j = 0; j < 100; ++j) {
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status = RREG32(UVD_STATUS);
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if (status & 2)
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break;
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mdelay(10);
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}
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r = 0;
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if (status & 2)
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break;
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DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
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WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET);
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mdelay(10);
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WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET);
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mdelay(10);
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r = -1;
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}
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if (r) {
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DRM_ERROR("UVD not responding, giving up!!!\n");
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return r;
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}
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/* enable interupt */
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WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));
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/* force RBC into idle state */
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WREG32(UVD_RBC_RB_CNTL, 0x11010101);
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/* Set the write pointer delay */
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WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
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/* program the 4GB memory segment for rptr and ring buffer */
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WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
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(0x7 << 16) | (0x1 << 31));
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/* Initialize the ring buffer's read and write pointers */
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WREG32(UVD_RBC_RB_RPTR, 0x0);
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ring->wptr = RREG32(UVD_RBC_RB_RPTR);
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WREG32(UVD_RBC_RB_WPTR, ring->wptr);
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/* set the ring address */
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WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);
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/* Set ring buffer size */
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rb_bufsz = order_base_2(ring->ring_size);
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rb_bufsz = (0x1 << 8) | rb_bufsz;
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WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
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return 0;
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}
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/**
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* uvd_v1_0_stop - stop UVD block
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*
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* @rdev: radeon_device pointer
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*
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* stop the UVD block
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*/
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void uvd_v1_0_stop(struct radeon_device *rdev)
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{
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/* force RBC into idle state */
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WREG32(UVD_RBC_RB_CNTL, 0x11010101);
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/* Stall UMC and register bus before resetting VCPU */
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WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
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WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
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mdelay(1);
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/* put VCPU into reset */
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WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
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mdelay(5);
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/* disable VCPU clock */
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WREG32(UVD_VCPU_CNTL, 0x0);
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/* Unstall UMC and register bus */
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WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
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WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
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}
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/**
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* uvd_v1_0_ring_test - register write test
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring pointer
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*
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* Test if we can successfully write to the context register
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*/
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int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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uint32_t tmp = 0;
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unsigned i;
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int r;
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WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD);
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r = radeon_ring_lock(rdev, ring, 3);
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if (r) {
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DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n",
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ring->idx, r);
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return r;
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}
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radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
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radeon_ring_write(ring, 0xDEADBEEF);
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radeon_ring_unlock_commit(rdev, ring, false);
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = RREG32(UVD_CONTEXT_ID);
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if (tmp == 0xDEADBEEF)
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break;
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udelay(1);
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}
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if (i < rdev->usec_timeout) {
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DRM_INFO("ring test on %d succeeded in %d usecs\n",
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ring->idx, i);
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} else {
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DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
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ring->idx, tmp);
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r = -EINVAL;
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}
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return r;
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}
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/**
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* uvd_v1_0_semaphore_emit - emit semaphore command
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring pointer
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* @semaphore: semaphore to emit commands for
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* @emit_wait: true if we should emit a wait command
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*
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* Emit a semaphore command (either wait or signal) to the UVD ring.
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*/
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bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
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struct radeon_ring *ring,
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struct radeon_semaphore *semaphore,
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bool emit_wait)
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{
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/* disable semaphores for UVD V1 hardware */
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return false;
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}
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/**
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* uvd_v1_0_ib_execute - execute indirect buffer
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*
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* @rdev: radeon_device pointer
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* @ib: indirect buffer to execute
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*
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* Write ring commands to execute the indirect buffer
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*/
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void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
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{
|
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struct radeon_ring *ring = &rdev->ring[ib->ring];
|
|
|
|
radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));
|
|
radeon_ring_write(ring, ib->gpu_addr);
|
|
radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));
|
|
radeon_ring_write(ring, ib->length_dw);
|
|
}
|
|
|
|
/**
|
|
* uvd_v1_0_ib_test - test ib execution
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @ring: radeon_ring pointer
|
|
*
|
|
* Test if we can successfully execute an IB
|
|
*/
|
|
int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|
{
|
|
struct radeon_fence *fence = NULL;
|
|
int r;
|
|
|
|
if (rdev->family < CHIP_RV740)
|
|
r = radeon_set_uvd_clocks(rdev, 10000, 10000);
|
|
else
|
|
r = radeon_set_uvd_clocks(rdev, 53300, 40000);
|
|
if (r) {
|
|
DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r);
|
|
return r;
|
|
}
|
|
|
|
r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
|
|
if (r) {
|
|
DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
|
|
goto error;
|
|
}
|
|
|
|
r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence);
|
|
if (r) {
|
|
DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
|
|
goto error;
|
|
}
|
|
|
|
r = radeon_fence_wait_timeout(fence, false, usecs_to_jiffies(
|
|
RADEON_USEC_IB_TEST_TIMEOUT));
|
|
if (r < 0) {
|
|
DRM_ERROR("radeon: fence wait failed (%d).\n", r);
|
|
goto error;
|
|
} else if (r == 0) {
|
|
DRM_ERROR("radeon: fence wait timed out.\n");
|
|
r = -ETIMEDOUT;
|
|
goto error;
|
|
}
|
|
r = 0;
|
|
DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
|
|
error:
|
|
radeon_fence_unref(&fence);
|
|
radeon_set_uvd_clocks(rdev, 0, 0);
|
|
return r;
|
|
}
|