Tao Zhou 88733d6801 drm/amdgpu: add register definition for VCN RAS initialization ... Prepare for enableing VCN RAS poison. v2: move SHIFT and MASK definitions to related sh_mask.h file. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-11-23 10:31:31 -05:00
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vcn_1_0_offset.h	drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headers	2019-03-19 15:36:48 -05:00
vcn_1_0_sh_mask.h	drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headers	2019-03-19 15:36:48 -05:00
vcn_2_0_0_offset.h	drm/amdgpu: add VCN 2.0 register headers	2019-06-20 15:54:33 -05:00
vcn_2_0_0_sh_mask.h	drm/amdgpu: add VCN 2.0 register headers	2019-06-20 15:54:33 -05:00
vcn_2_5_offset.h	drm/amdgpu: add register definition for VCN RAS initialization	2022-11-23 10:31:31 -05:00
vcn_2_5_sh_mask.h	drm/amdgpu: add register definition for VCN RAS initialization	2022-11-23 10:31:31 -05:00
vcn_2_6_0_offset.h	drm/amdgpu: add vcn v2_6_0 ip headers (v3)	2021-03-10 00:01:20 -05:00
vcn_2_6_0_sh_mask.h	drm/amdgpu: add vcn v2_6_0 ip headers (v3)	2021-03-10 00:01:20 -05:00
vcn_3_0_0_offset.h	drm/amdgpu: add VCN3.0 register headers (v2)	2020-06-03 13:51:55 -04:00
vcn_3_0_0_sh_mask.h	drm/amdgpu: add VCN 3.0 AV1 registers	2020-09-17 23:05:57 -04:00
vcn_4_0_0_offset.h	drm/amdgpu: add vcn 4_0_0 header files v7	2022-05-04 10:43:55 -04:00
vcn_4_0_0_sh_mask.h	drm/amdgpu: add vcn 4_0_0 header files v7	2022-05-04 10:43:55 -04:00