223 lines
5.7 KiB
Plaintext
223 lines
5.7 KiB
Plaintext
/*
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* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
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* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include "stih41x.dtsi"
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#include "stih415-clock.dtsi"
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#include "stih415-pinctrl.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset-controller/stih415-resets.h>
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/ {
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L2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0xfffe2000 0x1000>;
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arm,data-latency = <3 2 2>;
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arm,tag-latency = <1 1 1>;
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cache-unified;
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cache-level = <2>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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compatible = "simple-bus";
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powerdown: powerdown-controller {
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#reset-cells = <1>;
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compatible = "st,stih415-powerdown";
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};
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softreset: softreset-controller {
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#reset-cells = <1>;
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compatible = "st,stih415-softreset";
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};
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syscfg_sbc: sbc-syscfg@fe600000{
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compatible = "st,stih415-sbc-syscfg", "syscon";
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reg = <0xfe600000 0xb4>;
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};
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syscfg_front: front-syscfg@fee10000{
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compatible = "st,stih415-front-syscfg", "syscon";
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reg = <0xfee10000 0x194>;
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};
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syscfg_rear: rear-syscfg@fe830000{
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compatible = "st,stih415-rear-syscfg", "syscon";
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reg = <0xfe830000 0x190>;
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};
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/* MPE syscfgs */
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syscfg_left: left-syscfg@fd690000{
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compatible = "st,stih415-left-syscfg", "syscon";
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reg = <0xfd690000 0x78>;
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};
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syscfg_right: right-syscfg@fd320000{
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compatible = "st,stih415-right-syscfg", "syscon";
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reg = <0xfd320000 0x180>;
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};
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syscfg_system: system-syscfg@fdde0000 {
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compatible = "st,stih415-system-syscfg", "syscon";
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reg = <0xfdde0000 0x15c>;
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};
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syscfg_lpm: lpm-syscfg@fe4b5100{
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compatible = "st,stih415-lpm-syscfg", "syscon";
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reg = <0xfe4b5100 0x08>;
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};
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serial2: serial@fed32000 {
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compatible = "st,asc";
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status = "disabled";
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reg = <0xfed32000 0x2c>;
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interrupts = <0 197 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_serial2>;
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clocks = <&clk_s_a0_ls CLK_ICN_REG>;
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};
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/* SBC comms block ASCs in SASG1 */
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sbc_serial1: serial@fe531000 {
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compatible = "st,asc";
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status = "disabled";
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reg = <0xfe531000 0x2c>;
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interrupts = <0 210 0>;
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clocks = <&clk_sysin>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sbc_serial1>;
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};
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i2c@fed40000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0xfed40000 0x110>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_a0_ls CLK_ICN_REG>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0_default>;
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status = "disabled";
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};
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i2c@fed41000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0xfed41000 0x110>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_a0_ls CLK_ICN_REG>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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status = "disabled";
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};
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i2c@fe540000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0xfe540000 0x110>;
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interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_sysin>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sbc_i2c0_default>;
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status = "disabled";
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};
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i2c@fe541000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0xfe541000 0x110>;
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interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_sysin>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sbc_i2c1_default>;
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status = "disabled";
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};
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ethernet0: dwmac@fe810000 {
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device_type = "network";
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compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
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status = "disabled";
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reg = <0xfe810000 0x8000>, <0x148 0x4>;
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reg-names = "stmmaceth", "sti-ethconf";
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interrupts = <0 147 0>, <0 148 0>, <0 149 0>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
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resets = <&softreset STIH415_ETH0_SOFTRESET>;
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reset-names = "stmmaceth";
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snps,pbl = <32>;
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snps,mixed-burst;
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snps,force_sf_dma_mode;
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st,syscon = <&syscfg_rear>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mii0>;
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clock-names = "stmmaceth";
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clocks = <&clk_s_a1_ls CLK_GMAC0_PHY>;
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};
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ethernet1: dwmac@fef08000 {
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device_type = "network";
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compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
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status = "disabled";
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reg = <0xfef08000 0x8000>, <0x74 0x4>;
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reg-names = "stmmaceth", "sti-ethconf";
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interrupts = <0 150 0>, <0 151 0>, <0 152 0>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
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snps,pbl = <32>;
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snps,mixed-burst;
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snps,force_sf_dma_mode;
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st,syscon = <&syscfg_sbc>;
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resets = <&softreset STIH415_ETH1_SOFTRESET>;
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reset-names = "stmmaceth";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mii1>;
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clock-names = "stmmaceth";
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clocks = <&clk_s_a0_ls CLK_ETH1_PHY>;
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};
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rc: rc@fe518000 {
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compatible = "st,comms-irb";
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reg = <0xfe518000 0x234>;
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interrupts = <0 203 0>;
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clocks = <&clk_sysin>;
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rx-mode = "infrared";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ir>;
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resets = <&softreset STIH415_IRB_SOFTRESET>;
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};
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keyscan: keyscan@fe4b0000 {
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compatible = "st,sti-keyscan";
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status = "disabled";
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reg = <0xfe4b0000 0x2000>;
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interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>;
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clocks = <&clk_sysin>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_keyscan>;
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resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>,
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<&softreset STIH415_KEYSCAN_SOFTRESET>;
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};
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};
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};
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