560 lines
15 KiB
C
560 lines
15 KiB
C
/*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/clkdev.h>
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#include <asm/clkdev.h>
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#include <asm/div64.h>
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#include <mach/mx23.h>
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#include <mach/common.h>
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#include <mach/clock.h>
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#include "regs-clkctrl-mx23.h"
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#define CLKCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
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#define DIGCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
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#define PARENT_RATE_SHIFT 8
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static int _raw_clk_enable(struct clk *clk)
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{
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u32 reg;
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if (clk->enable_reg) {
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reg = __raw_readl(clk->enable_reg);
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reg &= ~(1 << clk->enable_shift);
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__raw_writel(reg, clk->enable_reg);
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}
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return 0;
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}
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static void _raw_clk_disable(struct clk *clk)
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{
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u32 reg;
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if (clk->enable_reg) {
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reg = __raw_readl(clk->enable_reg);
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reg |= 1 << clk->enable_shift;
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__raw_writel(reg, clk->enable_reg);
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}
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}
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/*
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* ref_xtal_clk
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*/
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static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
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{
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return 24000000;
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}
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static struct clk ref_xtal_clk = {
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.get_rate = ref_xtal_clk_get_rate,
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};
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/*
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* pll_clk
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*/
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static unsigned long pll_clk_get_rate(struct clk *clk)
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{
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return 480000000;
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}
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static int pll_clk_enable(struct clk *clk)
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{
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__raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
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BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
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CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET);
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/* Only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer
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* and is incorrect (excessive). Per definition of the PLLCTRL0
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* POWER field, waiting at least 10us.
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*/
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udelay(10);
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return 0;
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}
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static void pll_clk_disable(struct clk *clk)
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{
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__raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
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BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
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CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR);
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}
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static struct clk pll_clk = {
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.get_rate = pll_clk_get_rate,
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.enable = pll_clk_enable,
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.disable = pll_clk_disable,
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.parent = &ref_xtal_clk,
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};
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/*
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* ref_clk
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*/
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#define _CLK_GET_RATE_REF(name, sr, ss) \
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static unsigned long name##_get_rate(struct clk *clk) \
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{ \
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unsigned long parent_rate; \
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u32 reg, div; \
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\
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
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div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
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parent_rate = clk_get_rate(clk->parent); \
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\
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return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
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div, PARENT_RATE_SHIFT); \
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}
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_CLK_GET_RATE_REF(ref_cpu_clk, FRAC, CPU)
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_CLK_GET_RATE_REF(ref_emi_clk, FRAC, EMI)
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_CLK_GET_RATE_REF(ref_pix_clk, FRAC, PIX)
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_CLK_GET_RATE_REF(ref_io_clk, FRAC, IO)
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#define _DEFINE_CLOCK_REF(name, er, es) \
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static struct clk name = { \
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.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
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.enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
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.get_rate = name##_get_rate, \
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.enable = _raw_clk_enable, \
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.disable = _raw_clk_disable, \
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.parent = &pll_clk, \
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}
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_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC, CPU);
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_DEFINE_CLOCK_REF(ref_emi_clk, FRAC, EMI);
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_DEFINE_CLOCK_REF(ref_pix_clk, FRAC, PIX);
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_DEFINE_CLOCK_REF(ref_io_clk, FRAC, IO);
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/*
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* General clocks
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*
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* clk_get_rate
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*/
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static unsigned long rtc_clk_get_rate(struct clk *clk)
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{
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/* ref_xtal_clk is implemented as the only parent */
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return clk_get_rate(clk->parent) / 768;
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}
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static unsigned long clk32k_clk_get_rate(struct clk *clk)
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{
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return clk->parent->get_rate(clk->parent) / 750;
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}
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#define _CLK_GET_RATE(name, rs) \
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static unsigned long name##_get_rate(struct clk *clk) \
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{ \
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u32 reg, div; \
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\
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
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\
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if (clk->parent == &ref_xtal_clk) \
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div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
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BP_CLKCTRL_##rs##_DIV_XTAL; \
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else \
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div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
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BP_CLKCTRL_##rs##_DIV_##rs; \
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\
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if (!div) \
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return -EINVAL; \
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\
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return clk_get_rate(clk->parent) / div; \
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}
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_CLK_GET_RATE(cpu_clk, CPU)
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_CLK_GET_RATE(emi_clk, EMI)
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#define _CLK_GET_RATE1(name, rs) \
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static unsigned long name##_get_rate(struct clk *clk) \
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{ \
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u32 reg, div; \
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\
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
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div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
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\
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if (!div) \
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return -EINVAL; \
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\
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return clk_get_rate(clk->parent) / div; \
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}
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_CLK_GET_RATE1(hbus_clk, HBUS)
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_CLK_GET_RATE1(xbus_clk, XBUS)
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_CLK_GET_RATE1(ssp_clk, SSP)
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_CLK_GET_RATE1(gpmi_clk, GPMI)
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_CLK_GET_RATE1(lcdif_clk, PIX)
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#define _CLK_GET_RATE_STUB(name) \
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static unsigned long name##_get_rate(struct clk *clk) \
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{ \
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return clk_get_rate(clk->parent); \
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}
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_CLK_GET_RATE_STUB(uart_clk)
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_CLK_GET_RATE_STUB(audio_clk)
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_CLK_GET_RATE_STUB(pwm_clk)
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/*
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* clk_set_rate
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*/
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static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 reg, bm_busy, div_max, d, f, div, frac;
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unsigned long diff, parent_rate, calc_rate;
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int i;
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parent_rate = clk_get_rate(clk->parent);
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if (clk->parent == &ref_xtal_clk) {
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div_max = BM_CLKCTRL_CPU_DIV_XTAL >> BP_CLKCTRL_CPU_DIV_XTAL;
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bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;
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div = DIV_ROUND_UP(parent_rate, rate);
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if (div == 0 || div > div_max)
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return -EINVAL;
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} else {
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div_max = BM_CLKCTRL_CPU_DIV_CPU >> BP_CLKCTRL_CPU_DIV_CPU;
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bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;
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rate >>= PARENT_RATE_SHIFT;
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parent_rate >>= PARENT_RATE_SHIFT;
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diff = parent_rate;
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div = frac = 1;
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for (d = 1; d <= div_max; d++) {
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f = parent_rate * 18 / d / rate;
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if ((parent_rate * 18 / d) % rate)
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f++;
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if (f < 18 || f > 35)
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continue;
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calc_rate = parent_rate * 18 / f / d;
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if (calc_rate > rate)
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continue;
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if (rate - calc_rate < diff) {
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frac = f;
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div = d;
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diff = rate - calc_rate;
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}
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if (diff == 0)
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break;
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}
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if (diff == parent_rate)
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return -EINVAL;
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
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reg &= ~BM_CLKCTRL_FRAC_CPUFRAC;
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reg |= frac;
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__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
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}
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
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reg &= ~BM_CLKCTRL_CPU_DIV_CPU;
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reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
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__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
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for (i = 10000; i; i--)
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if (!(__raw_readl(CLKCTRL_BASE_ADDR +
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HW_CLKCTRL_CPU) & bm_busy))
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break;
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if (!i) {
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pr_err("%s: divider writing timeout\n", __func__);
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return -ETIMEDOUT;
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}
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return 0;
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}
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#define _CLK_SET_RATE(name, dr) \
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static int name##_set_rate(struct clk *clk, unsigned long rate) \
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{ \
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u32 reg, div_max, div; \
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unsigned long parent_rate; \
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int i; \
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\
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parent_rate = clk_get_rate(clk->parent); \
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div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
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\
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div = DIV_ROUND_UP(parent_rate, rate); \
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if (div == 0 || div > div_max) \
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return -EINVAL; \
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\
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
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reg &= ~BM_CLKCTRL_##dr##_DIV; \
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reg |= div << BP_CLKCTRL_##dr##_DIV; \
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if (reg & (1 << clk->enable_shift)) { \
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pr_err("%s: clock is gated\n", __func__); \
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return -EINVAL; \
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} \
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__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
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\
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for (i = 10000; i; i--) \
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if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
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HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \
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break; \
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if (!i) { \
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pr_err("%s: divider writing timeout\n", __func__); \
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return -ETIMEDOUT; \
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} \
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\
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return 0; \
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}
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_CLK_SET_RATE(xbus_clk, XBUS)
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_CLK_SET_RATE(ssp_clk, SSP)
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_CLK_SET_RATE(gpmi_clk, GPMI)
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_CLK_SET_RATE(lcdif_clk, PIX)
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#define _CLK_SET_RATE_STUB(name) \
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static int name##_set_rate(struct clk *clk, unsigned long rate) \
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{ \
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return -EINVAL; \
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}
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_CLK_SET_RATE_STUB(emi_clk)
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_CLK_SET_RATE_STUB(uart_clk)
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_CLK_SET_RATE_STUB(audio_clk)
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_CLK_SET_RATE_STUB(pwm_clk)
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_CLK_SET_RATE_STUB(clk32k_clk)
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/*
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* clk_set_parent
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*/
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#define _CLK_SET_PARENT(name, bit) \
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static int name##_set_parent(struct clk *clk, struct clk *parent) \
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{ \
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if (parent != clk->parent) { \
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__raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
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CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG); \
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clk->parent = parent; \
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} \
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\
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return 0; \
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}
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_CLK_SET_PARENT(cpu_clk, CPU)
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_CLK_SET_PARENT(emi_clk, EMI)
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_CLK_SET_PARENT(ssp_clk, SSP)
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_CLK_SET_PARENT(gpmi_clk, GPMI)
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_CLK_SET_PARENT(lcdif_clk, PIX)
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#define _CLK_SET_PARENT_STUB(name) \
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static int name##_set_parent(struct clk *clk, struct clk *parent) \
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{ \
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if (parent != clk->parent) \
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return -EINVAL; \
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else \
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return 0; \
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}
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_CLK_SET_PARENT_STUB(uart_clk)
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_CLK_SET_PARENT_STUB(audio_clk)
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_CLK_SET_PARENT_STUB(pwm_clk)
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_CLK_SET_PARENT_STUB(clk32k_clk)
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/*
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* clk definition
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*/
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static struct clk cpu_clk = {
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.get_rate = cpu_clk_get_rate,
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.set_rate = cpu_clk_set_rate,
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.set_parent = cpu_clk_set_parent,
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.parent = &ref_cpu_clk,
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};
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static struct clk hbus_clk = {
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.get_rate = hbus_clk_get_rate,
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.parent = &cpu_clk,
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};
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static struct clk xbus_clk = {
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.get_rate = xbus_clk_get_rate,
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.set_rate = xbus_clk_set_rate,
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.parent = &ref_xtal_clk,
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};
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static struct clk rtc_clk = {
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.get_rate = rtc_clk_get_rate,
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.parent = &ref_xtal_clk,
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};
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/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
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static struct clk usb_clk = {
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.enable_reg = DIGCTRL_BASE_ADDR,
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.enable_shift = 2,
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.enable = _raw_clk_enable,
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.disable = _raw_clk_disable,
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.parent = &pll_clk,
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};
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#define _DEFINE_CLOCK(name, er, es, p) \
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static struct clk name = { \
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.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
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.enable_shift = BP_CLKCTRL_##er##_##es, \
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.get_rate = name##_get_rate, \
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.set_rate = name##_set_rate, \
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.set_parent = name##_set_parent, \
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.enable = _raw_clk_enable, \
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.disable = _raw_clk_disable, \
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.parent = p, \
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}
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_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
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_DEFINE_CLOCK(ssp_clk, SSP, CLKGATE, &ref_xtal_clk);
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_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
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_DEFINE_CLOCK(lcdif_clk, PIX, CLKGATE, &ref_xtal_clk);
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_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
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_DEFINE_CLOCK(audio_clk, XTAL, FILT_CLK24M_GATE, &ref_xtal_clk);
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_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
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_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
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#define _REGISTER_CLOCK(d, n, c) \
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{ \
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.dev_id = d, \
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.con_id = n, \
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.clk = &c, \
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},
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static struct clk_lookup lookups[] = {
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/* for amba bus driver */
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_REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
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/* for amba-pl011 driver */
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_REGISTER_CLOCK("duart", NULL, uart_clk)
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_REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
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_REGISTER_CLOCK("rtc", NULL, rtc_clk)
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_REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
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_REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
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_REGISTER_CLOCK("mxs-mmc.0", NULL, ssp_clk)
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_REGISTER_CLOCK("mxs-mmc.1", NULL, ssp_clk)
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_REGISTER_CLOCK(NULL, "usb", usb_clk)
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_REGISTER_CLOCK(NULL, "audio", audio_clk)
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_REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
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_REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
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_REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
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_REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
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_REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
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_REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
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};
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static int clk_misc_init(void)
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{
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u32 reg;
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int i;
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/* Fix up parent per register setting */
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
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cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
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&ref_xtal_clk : &ref_cpu_clk;
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emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
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&ref_xtal_clk : &ref_emi_clk;
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ssp_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ?
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&ref_xtal_clk : &ref_io_clk;
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gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
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&ref_xtal_clk : &ref_io_clk;
|
|
lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) ?
|
|
&ref_xtal_clk : &ref_pix_clk;
|
|
|
|
/* Use int div over frac when both are available */
|
|
__raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
|
|
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
|
|
__raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
|
|
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
|
|
__raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
|
|
CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
|
|
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
|
|
reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
|
|
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
|
|
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
|
|
reg &= ~BM_CLKCTRL_SSP_DIV_FRAC_EN;
|
|
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
|
|
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
|
|
reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
|
|
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
|
|
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
|
|
reg &= ~BM_CLKCTRL_PIX_DIV_FRAC_EN;
|
|
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
|
|
|
|
/*
|
|
* Set safe hbus clock divider. A divider of 3 ensure that
|
|
* the Vddd voltage required for the cpu clock is sufficiently
|
|
* high for the hbus clock.
|
|
*/
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
|
|
reg &= BM_CLKCTRL_HBUS_DIV;
|
|
reg |= 3 << BP_CLKCTRL_HBUS_DIV;
|
|
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
|
|
|
|
for (i = 10000; i; i--)
|
|
if (!(__raw_readl(CLKCTRL_BASE_ADDR +
|
|
HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_BUSY))
|
|
break;
|
|
if (!i) {
|
|
pr_err("%s: divider writing timeout\n", __func__);
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
/* Gate off cpu clock in WFI for power saving */
|
|
__raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
|
|
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
|
|
|
|
/*
|
|
* 480 MHz seems too high to be ssp clock source directly,
|
|
* so set frac to get a 288 MHz ref_io.
|
|
*/
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
|
|
reg &= ~BM_CLKCTRL_FRAC_IOFRAC;
|
|
reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC;
|
|
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int __init mx23_clocks_init(void)
|
|
{
|
|
clk_misc_init();
|
|
|
|
/*
|
|
* source ssp clock from ref_io than ref_xtal,
|
|
* as ref_xtal only provides 24 MHz as maximum.
|
|
*/
|
|
clk_set_parent(&ssp_clk, &ref_io_clk);
|
|
|
|
clk_enable(&cpu_clk);
|
|
clk_enable(&hbus_clk);
|
|
clk_enable(&xbus_clk);
|
|
clk_enable(&emi_clk);
|
|
clk_enable(&uart_clk);
|
|
|
|
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
|
|
|
mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0);
|
|
|
|
return 0;
|
|
}
|