151 lines
3.4 KiB
C
151 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* SGMI module initialisation
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*
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* Copyright (C) 2014 Texas Instruments Incorporated
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* Authors: Sandeep Nair <sandeep_n@ti.com>
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* Sandeep Paulraj <s-paulraj@ti.com>
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* Wingman Kwok <w-kwok2@ti.com>
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*
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*/
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#include "netcp.h"
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#define SGMII_SRESET_RESET BIT(0)
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#define SGMII_SRESET_RTRESET BIT(1)
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#define SGMII_REG_STATUS_LOCK BIT(4)
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#define SGMII_REG_STATUS_LINK BIT(0)
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#define SGMII_REG_STATUS_AUTONEG BIT(2)
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#define SGMII_REG_CONTROL_AUTONEG BIT(0)
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#define SGMII23_OFFSET(x) ((x - 2) * 0x100)
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#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : (SGMII23_OFFSET(x)))
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/* SGMII registers */
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#define SGMII_SRESET_REG(x) (SGMII_OFFSET(x) + 0x004)
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#define SGMII_CTL_REG(x) (SGMII_OFFSET(x) + 0x010)
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#define SGMII_STATUS_REG(x) (SGMII_OFFSET(x) + 0x014)
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#define SGMII_MRADV_REG(x) (SGMII_OFFSET(x) + 0x018)
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static void sgmii_write_reg(void __iomem *base, int reg, u32 val)
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{
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writel(val, base + reg);
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}
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static u32 sgmii_read_reg(void __iomem *base, int reg)
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{
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return readl(base + reg);
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}
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static void sgmii_write_reg_bit(void __iomem *base, int reg, u32 val)
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{
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writel((readl(base + reg) | val), base + reg);
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}
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/* port is 0 based */
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int netcp_sgmii_reset(void __iomem *sgmii_ofs, int port)
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{
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/* Soft reset */
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sgmii_write_reg_bit(sgmii_ofs, SGMII_SRESET_REG(port),
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SGMII_SRESET_RESET);
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while ((sgmii_read_reg(sgmii_ofs, SGMII_SRESET_REG(port)) &
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SGMII_SRESET_RESET) != 0x0)
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;
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return 0;
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}
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/* port is 0 based */
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bool netcp_sgmii_rtreset(void __iomem *sgmii_ofs, int port, bool set)
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{
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u32 reg;
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bool oldval;
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/* Initiate a soft reset */
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reg = sgmii_read_reg(sgmii_ofs, SGMII_SRESET_REG(port));
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oldval = (reg & SGMII_SRESET_RTRESET) != 0x0;
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if (set)
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reg |= SGMII_SRESET_RTRESET;
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else
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reg &= ~SGMII_SRESET_RTRESET;
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sgmii_write_reg(sgmii_ofs, SGMII_SRESET_REG(port), reg);
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wmb();
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return oldval;
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}
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int netcp_sgmii_get_port_link(void __iomem *sgmii_ofs, int port)
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{
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u32 status = 0, link = 0;
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status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
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if ((status & SGMII_REG_STATUS_LINK) != 0)
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link = 1;
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return link;
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}
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int netcp_sgmii_config(void __iomem *sgmii_ofs, int port, u32 interface)
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{
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unsigned int i, status, mask;
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u32 mr_adv_ability;
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u32 control;
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switch (interface) {
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case SGMII_LINK_MAC_MAC_AUTONEG:
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mr_adv_ability = 0x9801;
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control = 0x21;
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break;
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case SGMII_LINK_MAC_PHY:
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case SGMII_LINK_MAC_PHY_NO_MDIO:
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mr_adv_ability = 1;
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control = 1;
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break;
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case SGMII_LINK_MAC_MAC_FORCED:
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mr_adv_ability = 0x9801;
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control = 0x20;
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break;
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case SGMII_LINK_MAC_FIBER:
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mr_adv_ability = 0x20;
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control = 0x1;
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break;
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default:
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WARN_ONCE(1, "Invalid sgmii interface: %d\n", interface);
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return -EINVAL;
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}
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sgmii_write_reg(sgmii_ofs, SGMII_CTL_REG(port), 0);
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/* Wait for the SerDes pll to lock */
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for (i = 0; i < 1000; i++) {
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usleep_range(1000, 2000);
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status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
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if ((status & SGMII_REG_STATUS_LOCK) != 0)
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break;
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}
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if ((status & SGMII_REG_STATUS_LOCK) == 0)
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pr_err("serdes PLL not locked\n");
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sgmii_write_reg(sgmii_ofs, SGMII_MRADV_REG(port), mr_adv_ability);
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sgmii_write_reg(sgmii_ofs, SGMII_CTL_REG(port), control);
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mask = SGMII_REG_STATUS_LINK;
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if (control & SGMII_REG_CONTROL_AUTONEG)
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mask |= SGMII_REG_STATUS_AUTONEG;
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for (i = 0; i < 1000; i++) {
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usleep_range(200, 500);
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status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
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if ((status & mask) == mask)
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break;
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}
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return 0;
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}
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