522 lines
12 KiB
C
522 lines
12 KiB
C
/*
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* SH RSPI driver
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*
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* Based on spi-sh.c:
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* Copyright (C) 2011 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/errno.h>
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#include <linux/list.h>
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/spi/spi.h>
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#define RSPI_SPCR 0x00
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#define RSPI_SSLP 0x01
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#define RSPI_SPPCR 0x02
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#define RSPI_SPSR 0x03
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#define RSPI_SPDR 0x04
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#define RSPI_SPSCR 0x08
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#define RSPI_SPSSR 0x09
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#define RSPI_SPBR 0x0a
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#define RSPI_SPDCR 0x0b
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#define RSPI_SPCKD 0x0c
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#define RSPI_SSLND 0x0d
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#define RSPI_SPND 0x0e
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#define RSPI_SPCR2 0x0f
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#define RSPI_SPCMD0 0x10
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#define RSPI_SPCMD1 0x12
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#define RSPI_SPCMD2 0x14
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#define RSPI_SPCMD3 0x16
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#define RSPI_SPCMD4 0x18
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#define RSPI_SPCMD5 0x1a
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#define RSPI_SPCMD6 0x1c
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#define RSPI_SPCMD7 0x1e
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/* SPCR */
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#define SPCR_SPRIE 0x80
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#define SPCR_SPE 0x40
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#define SPCR_SPTIE 0x20
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#define SPCR_SPEIE 0x10
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#define SPCR_MSTR 0x08
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#define SPCR_MODFEN 0x04
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#define SPCR_TXMD 0x02
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#define SPCR_SPMS 0x01
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/* SSLP */
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#define SSLP_SSL1P 0x02
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#define SSLP_SSL0P 0x01
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/* SPPCR */
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#define SPPCR_MOIFE 0x20
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#define SPPCR_MOIFV 0x10
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#define SPPCR_SPOM 0x04
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#define SPPCR_SPLP2 0x02
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#define SPPCR_SPLP 0x01
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/* SPSR */
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#define SPSR_SPRF 0x80
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#define SPSR_SPTEF 0x20
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#define SPSR_PERF 0x08
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#define SPSR_MODF 0x04
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#define SPSR_IDLNF 0x02
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#define SPSR_OVRF 0x01
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/* SPSCR */
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#define SPSCR_SPSLN_MASK 0x07
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/* SPSSR */
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#define SPSSR_SPECM_MASK 0x70
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#define SPSSR_SPCP_MASK 0x07
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/* SPDCR */
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#define SPDCR_SPLW 0x20
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#define SPDCR_SPRDTD 0x10
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#define SPDCR_SLSEL1 0x08
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#define SPDCR_SLSEL0 0x04
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#define SPDCR_SLSEL_MASK 0x0c
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#define SPDCR_SPFC1 0x02
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#define SPDCR_SPFC0 0x01
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/* SPCKD */
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#define SPCKD_SCKDL_MASK 0x07
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/* SSLND */
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#define SSLND_SLNDL_MASK 0x07
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/* SPND */
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#define SPND_SPNDL_MASK 0x07
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/* SPCR2 */
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#define SPCR2_PTE 0x08
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#define SPCR2_SPIE 0x04
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#define SPCR2_SPOE 0x02
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#define SPCR2_SPPE 0x01
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/* SPCMDn */
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#define SPCMD_SCKDEN 0x8000
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#define SPCMD_SLNDEN 0x4000
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#define SPCMD_SPNDEN 0x2000
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#define SPCMD_LSBF 0x1000
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#define SPCMD_SPB_MASK 0x0f00
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#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
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#define SPCMD_SPB_20BIT 0x0000
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#define SPCMD_SPB_24BIT 0x0100
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#define SPCMD_SPB_32BIT 0x0200
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#define SPCMD_SSLKP 0x0080
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#define SPCMD_SSLA_MASK 0x0030
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#define SPCMD_BRDV_MASK 0x000c
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#define SPCMD_CPOL 0x0002
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#define SPCMD_CPHA 0x0001
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struct rspi_data {
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void __iomem *addr;
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u32 max_speed_hz;
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struct spi_master *master;
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struct list_head queue;
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struct work_struct ws;
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wait_queue_head_t wait;
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spinlock_t lock;
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struct clk *clk;
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unsigned char spsr;
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};
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static void rspi_write8(struct rspi_data *rspi, u8 data, u16 offset)
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{
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iowrite8(data, rspi->addr + offset);
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}
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static void rspi_write16(struct rspi_data *rspi, u16 data, u16 offset)
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{
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iowrite16(data, rspi->addr + offset);
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}
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static u8 rspi_read8(struct rspi_data *rspi, u16 offset)
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{
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return ioread8(rspi->addr + offset);
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}
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static u16 rspi_read16(struct rspi_data *rspi, u16 offset)
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{
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return ioread16(rspi->addr + offset);
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}
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static unsigned char rspi_calc_spbr(struct rspi_data *rspi)
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{
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int tmp;
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unsigned char spbr;
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tmp = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
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spbr = clamp(tmp, 0, 255);
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return spbr;
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}
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static void rspi_enable_irq(struct rspi_data *rspi, u8 enable)
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{
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rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
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}
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static void rspi_disable_irq(struct rspi_data *rspi, u8 disable)
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{
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rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
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}
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static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
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u8 enable_bit)
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{
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int ret;
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rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
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rspi_enable_irq(rspi, enable_bit);
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ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
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if (ret == 0 && !(rspi->spsr & wait_mask))
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return -ETIMEDOUT;
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return 0;
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}
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static void rspi_assert_ssl(struct rspi_data *rspi)
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{
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rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
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}
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static void rspi_negate_ssl(struct rspi_data *rspi)
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{
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rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
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}
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static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
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{
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/* Sets output mode(CMOS) and MOSI signal(from previous transfer) */
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rspi_write8(rspi, 0x00, RSPI_SPPCR);
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/* Sets transfer bit rate */
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rspi_write8(rspi, rspi_calc_spbr(rspi), RSPI_SPBR);
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/* Sets number of frames to be used: 1 frame */
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rspi_write8(rspi, 0x00, RSPI_SPDCR);
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/* Sets RSPCK, SSL, next-access delay value */
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rspi_write8(rspi, 0x00, RSPI_SPCKD);
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rspi_write8(rspi, 0x00, RSPI_SSLND);
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rspi_write8(rspi, 0x00, RSPI_SPND);
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/* Sets parity, interrupt mask */
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rspi_write8(rspi, 0x00, RSPI_SPCR2);
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/* Sets SPCMD */
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rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP,
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RSPI_SPCMD0);
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/* Sets RSPI mode */
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rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
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return 0;
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}
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static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
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struct spi_transfer *t)
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{
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int remain = t->len;
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u8 *data;
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data = (u8 *)t->tx_buf;
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while (remain > 0) {
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rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
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RSPI_SPCR);
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if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
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dev_err(&rspi->master->dev,
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"%s: tx empty timeout\n", __func__);
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return -ETIMEDOUT;
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}
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rspi_write16(rspi, *data, RSPI_SPDR);
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data++;
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remain--;
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}
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/* Waiting for the last transmition */
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rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
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return 0;
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}
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static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
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struct spi_transfer *t)
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{
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int remain = t->len;
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u8 *data;
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unsigned char spsr;
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spsr = rspi_read8(rspi, RSPI_SPSR);
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if (spsr & SPSR_SPRF)
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rspi_read16(rspi, RSPI_SPDR); /* dummy read */
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if (spsr & SPSR_OVRF)
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rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
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RSPI_SPCR);
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data = (u8 *)t->rx_buf;
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while (remain > 0) {
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rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
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RSPI_SPCR);
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if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
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dev_err(&rspi->master->dev,
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"%s: tx empty timeout\n", __func__);
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return -ETIMEDOUT;
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}
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/* dummy write for generate clock */
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rspi_write16(rspi, 0x00, RSPI_SPDR);
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if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
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dev_err(&rspi->master->dev,
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"%s: receive timeout\n", __func__);
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return -ETIMEDOUT;
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}
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/* SPDR allows 16 or 32-bit access only */
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*data = (u8)rspi_read16(rspi, RSPI_SPDR);
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data++;
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remain--;
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}
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return 0;
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}
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static void rspi_work(struct work_struct *work)
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{
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struct rspi_data *rspi = container_of(work, struct rspi_data, ws);
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struct spi_message *mesg;
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struct spi_transfer *t;
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&rspi->lock, flags);
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while (!list_empty(&rspi->queue)) {
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mesg = list_entry(rspi->queue.next, struct spi_message, queue);
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list_del_init(&mesg->queue);
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spin_unlock_irqrestore(&rspi->lock, flags);
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rspi_assert_ssl(rspi);
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list_for_each_entry(t, &mesg->transfers, transfer_list) {
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if (t->tx_buf) {
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ret = rspi_send_pio(rspi, mesg, t);
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if (ret < 0)
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goto error;
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}
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if (t->rx_buf) {
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ret = rspi_receive_pio(rspi, mesg, t);
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if (ret < 0)
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goto error;
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}
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mesg->actual_length += t->len;
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}
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rspi_negate_ssl(rspi);
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mesg->status = 0;
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mesg->complete(mesg->context);
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spin_lock_irqsave(&rspi->lock, flags);
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}
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return;
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error:
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mesg->status = ret;
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mesg->complete(mesg->context);
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}
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static int rspi_setup(struct spi_device *spi)
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{
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struct rspi_data *rspi = spi_master_get_devdata(spi->master);
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if (!spi->bits_per_word)
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spi->bits_per_word = 8;
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rspi->max_speed_hz = spi->max_speed_hz;
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rspi_set_config_register(rspi, 8);
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return 0;
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}
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static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg)
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{
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struct rspi_data *rspi = spi_master_get_devdata(spi->master);
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unsigned long flags;
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mesg->actual_length = 0;
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mesg->status = -EINPROGRESS;
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spin_lock_irqsave(&rspi->lock, flags);
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list_add_tail(&mesg->queue, &rspi->queue);
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schedule_work(&rspi->ws);
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spin_unlock_irqrestore(&rspi->lock, flags);
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return 0;
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}
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static void rspi_cleanup(struct spi_device *spi)
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{
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}
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static irqreturn_t rspi_irq(int irq, void *_sr)
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{
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struct rspi_data *rspi = (struct rspi_data *)_sr;
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unsigned long spsr;
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irqreturn_t ret = IRQ_NONE;
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unsigned char disable_irq = 0;
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rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
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if (spsr & SPSR_SPRF)
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disable_irq |= SPCR_SPRIE;
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if (spsr & SPSR_SPTEF)
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disable_irq |= SPCR_SPTIE;
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if (disable_irq) {
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ret = IRQ_HANDLED;
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rspi_disable_irq(rspi, disable_irq);
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wake_up(&rspi->wait);
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}
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return ret;
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}
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static int __devexit rspi_remove(struct platform_device *pdev)
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{
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struct rspi_data *rspi = dev_get_drvdata(&pdev->dev);
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spi_unregister_master(rspi->master);
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free_irq(platform_get_irq(pdev, 0), rspi);
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clk_put(rspi->clk);
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iounmap(rspi->addr);
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spi_master_put(rspi->master);
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return 0;
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}
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static int __devinit rspi_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct spi_master *master;
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struct rspi_data *rspi;
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int ret, irq;
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char clk_name[16];
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/* get base addr */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (unlikely(res == NULL)) {
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dev_err(&pdev->dev, "invalid resource\n");
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return -EINVAL;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "platform_get_irq error\n");
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return -ENODEV;
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}
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master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
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if (master == NULL) {
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dev_err(&pdev->dev, "spi_alloc_master error.\n");
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return -ENOMEM;
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}
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rspi = spi_master_get_devdata(master);
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dev_set_drvdata(&pdev->dev, rspi);
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rspi->master = master;
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rspi->addr = ioremap(res->start, resource_size(res));
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if (rspi->addr == NULL) {
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dev_err(&pdev->dev, "ioremap error.\n");
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ret = -ENOMEM;
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goto error1;
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}
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snprintf(clk_name, sizeof(clk_name), "rspi%d", pdev->id);
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rspi->clk = clk_get(&pdev->dev, clk_name);
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if (IS_ERR(rspi->clk)) {
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dev_err(&pdev->dev, "cannot get clock\n");
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ret = PTR_ERR(rspi->clk);
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goto error2;
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}
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clk_enable(rspi->clk);
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INIT_LIST_HEAD(&rspi->queue);
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spin_lock_init(&rspi->lock);
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INIT_WORK(&rspi->ws, rspi_work);
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init_waitqueue_head(&rspi->wait);
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master->num_chipselect = 2;
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master->bus_num = pdev->id;
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master->setup = rspi_setup;
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master->transfer = rspi_transfer;
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master->cleanup = rspi_cleanup;
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ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi);
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if (ret < 0) {
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dev_err(&pdev->dev, "request_irq error\n");
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goto error3;
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}
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ret = spi_register_master(master);
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if (ret < 0) {
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dev_err(&pdev->dev, "spi_register_master error.\n");
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goto error4;
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}
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dev_info(&pdev->dev, "probed\n");
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return 0;
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error4:
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free_irq(irq, rspi);
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error3:
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clk_put(rspi->clk);
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error2:
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iounmap(rspi->addr);
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error1:
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spi_master_put(master);
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|
return ret;
|
|
}
|
|
|
|
static struct platform_driver rspi_driver = {
|
|
.probe = rspi_probe,
|
|
.remove = __devexit_p(rspi_remove),
|
|
.driver = {
|
|
.name = "rspi",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
module_platform_driver(rspi_driver);
|
|
|
|
MODULE_DESCRIPTION("Renesas RSPI bus driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Yoshihiro Shimoda");
|
|
MODULE_ALIAS("platform:rspi");
|