220 lines
4.4 KiB
C
220 lines
4.4 KiB
C
#ifndef DIBX000_COMMON_H
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#define DIBX000_COMMON_H
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enum dibx000_i2c_interface {
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DIBX000_I2C_INTERFACE_TUNER = 0,
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DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
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DIBX000_I2C_INTERFACE_GPIO_3_4 = 2
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};
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struct dibx000_i2c_master {
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#define DIB3000MC 1
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#define DIB7000 2
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#define DIB7000P 11
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#define DIB7000MC 12
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#define DIB8000 13
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u16 device_rev;
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enum dibx000_i2c_interface selected_interface;
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// struct i2c_adapter tuner_i2c_adap;
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struct i2c_adapter gated_tuner_i2c_adap;
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struct i2c_adapter *i2c_adap;
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u8 i2c_addr;
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u16 base_reg;
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};
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extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst,
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u16 device_rev, struct i2c_adapter *i2c_adap,
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u8 i2c_addr);
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extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
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*mst,
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enum dibx000_i2c_interface
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intf, int gating);
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extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
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extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
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extern u32 systime(void);
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#define BAND_LBAND 0x01
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#define BAND_UHF 0x02
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#define BAND_VHF 0x04
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#define BAND_SBAND 0x08
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#define BAND_FM 0x10
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#define BAND_CBAND 0x20
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#define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
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(freq_kHz) <= 115000 ? BAND_FM : \
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(freq_kHz) <= 250000 ? BAND_VHF : \
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(freq_kHz) <= 863000 ? BAND_UHF : \
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(freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND )
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struct dibx000_agc_config {
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/* defines the capabilities of this AGC-setting - using the BAND_-defines */
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u8 band_caps;
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u16 setup;
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u16 inv_gain;
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u16 time_stabiliz;
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u8 alpha_level;
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u16 thlock;
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u8 wbd_inv;
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u16 wbd_ref;
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u8 wbd_sel;
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u8 wbd_alpha;
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u16 agc1_max;
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u16 agc1_min;
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u16 agc2_max;
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u16 agc2_min;
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u8 agc1_pt1;
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u8 agc1_pt2;
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u8 agc1_pt3;
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u8 agc1_slope1;
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u8 agc1_slope2;
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u8 agc2_pt1;
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u8 agc2_pt2;
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u8 agc2_slope1;
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u8 agc2_slope2;
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u8 alpha_mant;
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u8 alpha_exp;
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u8 beta_mant;
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u8 beta_exp;
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u8 perform_agc_softsplit;
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struct {
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u16 min;
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u16 max;
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u16 min_thres;
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u16 max_thres;
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} split;
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};
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struct dibx000_bandwidth_config {
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u32 internal;
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u32 sampling;
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u8 pll_prediv;
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u8 pll_ratio;
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u8 pll_range;
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u8 pll_reset;
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u8 pll_bypass;
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u8 enable_refdiv;
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u8 bypclk_div;
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u8 IO_CLK_en_core;
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u8 ADClkSrc;
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u8 modulo;
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u16 sad_cfg;
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u32 ifreq;
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u32 timf;
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u32 xtal_hz;
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};
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enum dibx000_adc_states {
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DIBX000_SLOW_ADC_ON = 0,
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DIBX000_SLOW_ADC_OFF,
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DIBX000_ADC_ON,
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DIBX000_ADC_OFF,
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DIBX000_VBG_ENABLE,
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DIBX000_VBG_DISABLE,
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};
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#define BANDWIDTH_TO_KHZ(v) ( (v) == BANDWIDTH_8_MHZ ? 8000 : \
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(v) == BANDWIDTH_7_MHZ ? 7000 : \
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(v) == BANDWIDTH_6_MHZ ? 6000 : 8000 )
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#define BANDWIDTH_TO_INDEX(v) ( \
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(v) == 8000 ? BANDWIDTH_8_MHZ : \
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(v) == 7000 ? BANDWIDTH_7_MHZ : \
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(v) == 6000 ? BANDWIDTH_6_MHZ : BANDWIDTH_8_MHZ )
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/* Chip output mode. */
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#define OUTMODE_HIGH_Z 0
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#define OUTMODE_MPEG2_PAR_GATED_CLK 1
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#define OUTMODE_MPEG2_PAR_CONT_CLK 2
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#define OUTMODE_MPEG2_SERIAL 7
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#define OUTMODE_DIVERSITY 4
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#define OUTMODE_MPEG2_FIFO 5
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#define OUTMODE_ANALOG_ADC 6
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enum frontend_tune_state {
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CT_TUNER_START = 10,
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CT_TUNER_STEP_0,
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CT_TUNER_STEP_1,
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CT_TUNER_STEP_2,
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CT_TUNER_STEP_3,
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CT_TUNER_STEP_4,
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CT_TUNER_STEP_5,
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CT_TUNER_STEP_6,
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CT_TUNER_STEP_7,
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CT_TUNER_STOP,
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CT_AGC_START = 20,
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CT_AGC_STEP_0,
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CT_AGC_STEP_1,
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CT_AGC_STEP_2,
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CT_AGC_STEP_3,
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CT_AGC_STEP_4,
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CT_AGC_STOP,
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CT_DEMOD_START = 30,
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CT_DEMOD_STEP_1,
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CT_DEMOD_STEP_2,
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CT_DEMOD_STEP_3,
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CT_DEMOD_STEP_4,
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CT_DEMOD_STEP_5,
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CT_DEMOD_STEP_6,
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CT_DEMOD_STEP_7,
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CT_DEMOD_STEP_8,
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CT_DEMOD_STEP_9,
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CT_DEMOD_STEP_10,
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CT_DEMOD_SEARCH_NEXT = 41,
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CT_DEMOD_STEP_LOCKED,
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CT_DEMOD_STOP,
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CT_DONE = 100,
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CT_SHUTDOWN,
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};
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struct dvb_frontend_parametersContext {
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#define CHANNEL_STATUS_PARAMETERS_UNKNOWN 0x01
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#define CHANNEL_STATUS_PARAMETERS_SET 0x02
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u8 status;
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u32 tune_time_estimation[2];
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s32 tps_available;
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u16 tps[9];
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};
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#define FE_STATUS_TUNE_FAILED 0
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#define FE_STATUS_TUNE_TIMED_OUT -1
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#define FE_STATUS_TUNE_TIME_TOO_SHORT -2
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#define FE_STATUS_TUNE_PENDING -3
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#define FE_STATUS_STD_SUCCESS -4
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#define FE_STATUS_FFT_SUCCESS -5
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#define FE_STATUS_DEMOD_SUCCESS -6
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#define FE_STATUS_LOCKED -7
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#define FE_STATUS_DATA_LOCKED -8
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#define FE_CALLBACK_TIME_NEVER 0xffffffff
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#define ABS(x) ((x < 0) ? (-x) : (x))
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#endif
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