1003 lines
25 KiB
C
1003 lines
25 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/console.h>
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#include <linux/vgaarb.h>
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#include <linux/vga_switcheroo.h>
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#include <drm/drm_drv.h>
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#include "display/intel_fbdev.h"
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#include "i915_drv.h"
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#include "i915_globals.h"
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#include "i915_selftest.h"
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#define PLATFORM(x) .platform = (x)
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#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
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#define I845_PIPE_OFFSETS \
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.pipe_offsets = { \
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[TRANSCODER_A] = PIPE_A_OFFSET, \
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}, \
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.trans_offsets = { \
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[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
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}
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#define I9XX_PIPE_OFFSETS \
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.pipe_offsets = { \
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[TRANSCODER_A] = PIPE_A_OFFSET, \
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[TRANSCODER_B] = PIPE_B_OFFSET, \
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}, \
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.trans_offsets = { \
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[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
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[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
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}
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#define IVB_PIPE_OFFSETS \
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.pipe_offsets = { \
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[TRANSCODER_A] = PIPE_A_OFFSET, \
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[TRANSCODER_B] = PIPE_B_OFFSET, \
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[TRANSCODER_C] = PIPE_C_OFFSET, \
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}, \
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.trans_offsets = { \
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[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
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[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
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[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
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}
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#define HSW_PIPE_OFFSETS \
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.pipe_offsets = { \
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[TRANSCODER_A] = PIPE_A_OFFSET, \
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[TRANSCODER_B] = PIPE_B_OFFSET, \
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[TRANSCODER_C] = PIPE_C_OFFSET, \
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[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
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}, \
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.trans_offsets = { \
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[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
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[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
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[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
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[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
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}
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#define CHV_PIPE_OFFSETS \
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.pipe_offsets = { \
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[TRANSCODER_A] = PIPE_A_OFFSET, \
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[TRANSCODER_B] = PIPE_B_OFFSET, \
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[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
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}, \
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.trans_offsets = { \
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[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
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[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
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[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
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}
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#define I845_CURSOR_OFFSETS \
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.cursor_offsets = { \
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[PIPE_A] = CURSOR_A_OFFSET, \
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}
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#define I9XX_CURSOR_OFFSETS \
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.cursor_offsets = { \
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[PIPE_A] = CURSOR_A_OFFSET, \
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[PIPE_B] = CURSOR_B_OFFSET, \
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}
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#define CHV_CURSOR_OFFSETS \
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.cursor_offsets = { \
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[PIPE_A] = CURSOR_A_OFFSET, \
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[PIPE_B] = CURSOR_B_OFFSET, \
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[PIPE_C] = CHV_CURSOR_C_OFFSET, \
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}
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#define IVB_CURSOR_OFFSETS \
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.cursor_offsets = { \
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[PIPE_A] = CURSOR_A_OFFSET, \
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[PIPE_B] = IVB_CURSOR_B_OFFSET, \
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[PIPE_C] = IVB_CURSOR_C_OFFSET, \
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}
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#define I9XX_COLORS \
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.color = { .gamma_lut_size = 256 }
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#define I965_COLORS \
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.color = { .gamma_lut_size = 129, \
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.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
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}
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#define ILK_COLORS \
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.color = { .gamma_lut_size = 1024 }
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#define IVB_COLORS \
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.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
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#define CHV_COLORS \
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.color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
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.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
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.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
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}
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#define GLK_COLORS \
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.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
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.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
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DRM_COLOR_LUT_EQUAL_CHANNELS, \
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}
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/* Keep in gen based order, and chronological order within a gen */
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#define GEN_DEFAULT_PAGE_SIZES \
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.page_sizes = I915_GTT_PAGE_SIZE_4K
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#define I830_FEATURES \
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GEN(2), \
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.is_mobile = 1, \
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.num_pipes = 2, \
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.display.has_overlay = 1, \
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.display.cursor_needs_physical = 1, \
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.display.overlay_needs_physical = 1, \
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.display.has_gmch = 1, \
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.gpu_reset_clobbers_display = true, \
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.hws_needs_physical = 1, \
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.unfenced_needs_alignment = 1, \
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.engine_mask = BIT(RCS0), \
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.has_snoop = true, \
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.has_coherent_ggtt = false, \
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I9XX_PIPE_OFFSETS, \
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I9XX_CURSOR_OFFSETS, \
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I9XX_COLORS, \
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GEN_DEFAULT_PAGE_SIZES
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#define I845_FEATURES \
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GEN(2), \
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.num_pipes = 1, \
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.display.has_overlay = 1, \
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.display.overlay_needs_physical = 1, \
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.display.has_gmch = 1, \
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.gpu_reset_clobbers_display = true, \
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.hws_needs_physical = 1, \
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.unfenced_needs_alignment = 1, \
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.engine_mask = BIT(RCS0), \
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.has_snoop = true, \
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.has_coherent_ggtt = false, \
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I845_PIPE_OFFSETS, \
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I845_CURSOR_OFFSETS, \
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I9XX_COLORS, \
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GEN_DEFAULT_PAGE_SIZES
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static const struct intel_device_info intel_i830_info = {
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I830_FEATURES,
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PLATFORM(INTEL_I830),
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};
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static const struct intel_device_info intel_i845g_info = {
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I845_FEATURES,
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PLATFORM(INTEL_I845G),
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};
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static const struct intel_device_info intel_i85x_info = {
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I830_FEATURES,
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PLATFORM(INTEL_I85X),
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.display.has_fbc = 1,
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};
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static const struct intel_device_info intel_i865g_info = {
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I845_FEATURES,
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PLATFORM(INTEL_I865G),
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};
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#define GEN3_FEATURES \
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GEN(3), \
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.num_pipes = 2, \
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.display.has_gmch = 1, \
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.gpu_reset_clobbers_display = true, \
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.engine_mask = BIT(RCS0), \
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.has_snoop = true, \
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.has_coherent_ggtt = true, \
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I9XX_PIPE_OFFSETS, \
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I9XX_CURSOR_OFFSETS, \
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I9XX_COLORS, \
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GEN_DEFAULT_PAGE_SIZES
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static const struct intel_device_info intel_i915g_info = {
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GEN3_FEATURES,
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PLATFORM(INTEL_I915G),
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.has_coherent_ggtt = false,
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.display.cursor_needs_physical = 1,
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.display.has_overlay = 1,
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.display.overlay_needs_physical = 1,
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.hws_needs_physical = 1,
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.unfenced_needs_alignment = 1,
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};
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static const struct intel_device_info intel_i915gm_info = {
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GEN3_FEATURES,
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PLATFORM(INTEL_I915GM),
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.is_mobile = 1,
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.display.cursor_needs_physical = 1,
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.display.has_overlay = 1,
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.display.overlay_needs_physical = 1,
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.display.supports_tv = 1,
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.display.has_fbc = 1,
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.hws_needs_physical = 1,
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.unfenced_needs_alignment = 1,
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};
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static const struct intel_device_info intel_i945g_info = {
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GEN3_FEATURES,
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PLATFORM(INTEL_I945G),
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.display.has_hotplug = 1,
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.display.cursor_needs_physical = 1,
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.display.has_overlay = 1,
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.display.overlay_needs_physical = 1,
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.hws_needs_physical = 1,
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.unfenced_needs_alignment = 1,
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};
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static const struct intel_device_info intel_i945gm_info = {
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GEN3_FEATURES,
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PLATFORM(INTEL_I945GM),
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.is_mobile = 1,
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.display.has_hotplug = 1,
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.display.cursor_needs_physical = 1,
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.display.has_overlay = 1,
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.display.overlay_needs_physical = 1,
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.display.supports_tv = 1,
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.display.has_fbc = 1,
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.hws_needs_physical = 1,
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.unfenced_needs_alignment = 1,
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};
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static const struct intel_device_info intel_g33_info = {
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GEN3_FEATURES,
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PLATFORM(INTEL_G33),
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.display.has_hotplug = 1,
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.display.has_overlay = 1,
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};
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static const struct intel_device_info intel_pineview_g_info = {
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GEN3_FEATURES,
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PLATFORM(INTEL_PINEVIEW),
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.display.has_hotplug = 1,
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.display.has_overlay = 1,
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};
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static const struct intel_device_info intel_pineview_m_info = {
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GEN3_FEATURES,
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PLATFORM(INTEL_PINEVIEW),
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.is_mobile = 1,
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.display.has_hotplug = 1,
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.display.has_overlay = 1,
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};
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#define GEN4_FEATURES \
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GEN(4), \
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.num_pipes = 2, \
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.display.has_hotplug = 1, \
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.display.has_gmch = 1, \
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.gpu_reset_clobbers_display = true, \
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.engine_mask = BIT(RCS0), \
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.has_snoop = true, \
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.has_coherent_ggtt = true, \
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I9XX_PIPE_OFFSETS, \
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I9XX_CURSOR_OFFSETS, \
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I965_COLORS, \
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GEN_DEFAULT_PAGE_SIZES
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static const struct intel_device_info intel_i965g_info = {
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GEN4_FEATURES,
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PLATFORM(INTEL_I965G),
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.display.has_overlay = 1,
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.hws_needs_physical = 1,
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.has_snoop = false,
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};
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static const struct intel_device_info intel_i965gm_info = {
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GEN4_FEATURES,
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PLATFORM(INTEL_I965GM),
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.is_mobile = 1,
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.display.has_fbc = 1,
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.display.has_overlay = 1,
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.display.supports_tv = 1,
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.hws_needs_physical = 1,
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.has_snoop = false,
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};
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static const struct intel_device_info intel_g45_info = {
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GEN4_FEATURES,
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PLATFORM(INTEL_G45),
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.engine_mask = BIT(RCS0) | BIT(VCS0),
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.gpu_reset_clobbers_display = false,
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};
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static const struct intel_device_info intel_gm45_info = {
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GEN4_FEATURES,
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PLATFORM(INTEL_GM45),
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.is_mobile = 1,
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.display.has_fbc = 1,
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.display.supports_tv = 1,
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.engine_mask = BIT(RCS0) | BIT(VCS0),
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.gpu_reset_clobbers_display = false,
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};
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#define GEN5_FEATURES \
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GEN(5), \
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.num_pipes = 2, \
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.display.has_hotplug = 1, \
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.engine_mask = BIT(RCS0) | BIT(VCS0), \
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.has_snoop = true, \
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.has_coherent_ggtt = true, \
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/* ilk does support rc6, but we do not implement [power] contexts */ \
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.has_rc6 = 0, \
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I9XX_PIPE_OFFSETS, \
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I9XX_CURSOR_OFFSETS, \
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ILK_COLORS, \
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GEN_DEFAULT_PAGE_SIZES
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static const struct intel_device_info intel_ironlake_d_info = {
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GEN5_FEATURES,
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PLATFORM(INTEL_IRONLAKE),
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};
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static const struct intel_device_info intel_ironlake_m_info = {
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GEN5_FEATURES,
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PLATFORM(INTEL_IRONLAKE),
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.is_mobile = 1,
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.display.has_fbc = 1,
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};
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#define GEN6_FEATURES \
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GEN(6), \
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.num_pipes = 2, \
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.display.has_hotplug = 1, \
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.display.has_fbc = 1, \
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.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
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.has_coherent_ggtt = true, \
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.has_llc = 1, \
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.has_rc6 = 1, \
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.has_rc6p = 1, \
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.has_rps = true, \
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.ppgtt_type = INTEL_PPGTT_ALIASING, \
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.ppgtt_size = 31, \
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I9XX_PIPE_OFFSETS, \
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I9XX_CURSOR_OFFSETS, \
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ILK_COLORS, \
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GEN_DEFAULT_PAGE_SIZES
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#define SNB_D_PLATFORM \
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GEN6_FEATURES, \
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PLATFORM(INTEL_SANDYBRIDGE)
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static const struct intel_device_info intel_sandybridge_d_gt1_info = {
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SNB_D_PLATFORM,
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.gt = 1,
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};
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static const struct intel_device_info intel_sandybridge_d_gt2_info = {
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SNB_D_PLATFORM,
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.gt = 2,
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};
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#define SNB_M_PLATFORM \
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GEN6_FEATURES, \
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PLATFORM(INTEL_SANDYBRIDGE), \
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.is_mobile = 1
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static const struct intel_device_info intel_sandybridge_m_gt1_info = {
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SNB_M_PLATFORM,
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.gt = 1,
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};
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static const struct intel_device_info intel_sandybridge_m_gt2_info = {
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SNB_M_PLATFORM,
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.gt = 2,
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};
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#define GEN7_FEATURES \
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GEN(7), \
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.num_pipes = 3, \
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.display.has_hotplug = 1, \
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.display.has_fbc = 1, \
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.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
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.has_coherent_ggtt = true, \
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.has_llc = 1, \
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.has_rc6 = 1, \
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.has_rc6p = 1, \
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.has_rps = true, \
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.ppgtt_type = INTEL_PPGTT_FULL, \
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.ppgtt_size = 31, \
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IVB_PIPE_OFFSETS, \
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IVB_CURSOR_OFFSETS, \
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IVB_COLORS, \
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GEN_DEFAULT_PAGE_SIZES
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#define IVB_D_PLATFORM \
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GEN7_FEATURES, \
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PLATFORM(INTEL_IVYBRIDGE), \
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.has_l3_dpf = 1
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static const struct intel_device_info intel_ivybridge_d_gt1_info = {
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IVB_D_PLATFORM,
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.gt = 1,
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};
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static const struct intel_device_info intel_ivybridge_d_gt2_info = {
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IVB_D_PLATFORM,
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.gt = 2,
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};
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#define IVB_M_PLATFORM \
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GEN7_FEATURES, \
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PLATFORM(INTEL_IVYBRIDGE), \
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.is_mobile = 1, \
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.has_l3_dpf = 1
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static const struct intel_device_info intel_ivybridge_m_gt1_info = {
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IVB_M_PLATFORM,
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.gt = 1,
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};
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static const struct intel_device_info intel_ivybridge_m_gt2_info = {
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IVB_M_PLATFORM,
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.gt = 2,
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};
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static const struct intel_device_info intel_ivybridge_q_info = {
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GEN7_FEATURES,
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PLATFORM(INTEL_IVYBRIDGE),
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.gt = 2,
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.num_pipes = 0, /* legal, last one wins */
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.has_l3_dpf = 1,
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};
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static const struct intel_device_info intel_valleyview_info = {
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PLATFORM(INTEL_VALLEYVIEW),
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GEN(7),
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.is_lp = 1,
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.num_pipes = 2,
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.has_runtime_pm = 1,
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.has_rc6 = 1,
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.has_rps = true,
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.display.has_gmch = 1,
|
|
.display.has_hotplug = 1,
|
|
.ppgtt_type = INTEL_PPGTT_FULL,
|
|
.ppgtt_size = 31,
|
|
.has_snoop = true,
|
|
.has_coherent_ggtt = false,
|
|
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
|
|
.display_mmio_offset = VLV_DISPLAY_BASE,
|
|
I9XX_PIPE_OFFSETS,
|
|
I9XX_CURSOR_OFFSETS,
|
|
I965_COLORS,
|
|
GEN_DEFAULT_PAGE_SIZES,
|
|
};
|
|
|
|
#define G75_FEATURES \
|
|
GEN7_FEATURES, \
|
|
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
|
|
.display.has_ddi = 1, \
|
|
.has_fpga_dbg = 1, \
|
|
.display.has_psr = 1, \
|
|
.display.has_dp_mst = 1, \
|
|
.has_rc6p = 0 /* RC6p removed-by HSW */, \
|
|
HSW_PIPE_OFFSETS, \
|
|
.has_runtime_pm = 1
|
|
|
|
#define HSW_PLATFORM \
|
|
G75_FEATURES, \
|
|
PLATFORM(INTEL_HASWELL), \
|
|
.has_l3_dpf = 1
|
|
|
|
static const struct intel_device_info intel_haswell_gt1_info = {
|
|
HSW_PLATFORM,
|
|
.gt = 1,
|
|
};
|
|
|
|
static const struct intel_device_info intel_haswell_gt2_info = {
|
|
HSW_PLATFORM,
|
|
.gt = 2,
|
|
};
|
|
|
|
static const struct intel_device_info intel_haswell_gt3_info = {
|
|
HSW_PLATFORM,
|
|
.gt = 3,
|
|
};
|
|
|
|
#define GEN8_FEATURES \
|
|
G75_FEATURES, \
|
|
GEN(8), \
|
|
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
|
|
I915_GTT_PAGE_SIZE_2M, \
|
|
.has_logical_ring_contexts = 1, \
|
|
.ppgtt_type = INTEL_PPGTT_FULL, \
|
|
.ppgtt_size = 48, \
|
|
.has_64bit_reloc = 1, \
|
|
.has_reset_engine = 1
|
|
|
|
#define BDW_PLATFORM \
|
|
GEN8_FEATURES, \
|
|
PLATFORM(INTEL_BROADWELL)
|
|
|
|
static const struct intel_device_info intel_broadwell_gt1_info = {
|
|
BDW_PLATFORM,
|
|
.gt = 1,
|
|
};
|
|
|
|
static const struct intel_device_info intel_broadwell_gt2_info = {
|
|
BDW_PLATFORM,
|
|
.gt = 2,
|
|
};
|
|
|
|
static const struct intel_device_info intel_broadwell_rsvd_info = {
|
|
BDW_PLATFORM,
|
|
.gt = 3,
|
|
/* According to the device ID those devices are GT3, they were
|
|
* previously treated as not GT3, keep it like that.
|
|
*/
|
|
};
|
|
|
|
static const struct intel_device_info intel_broadwell_gt3_info = {
|
|
BDW_PLATFORM,
|
|
.gt = 3,
|
|
.engine_mask =
|
|
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
|
|
};
|
|
|
|
static const struct intel_device_info intel_cherryview_info = {
|
|
PLATFORM(INTEL_CHERRYVIEW),
|
|
GEN(8),
|
|
.num_pipes = 3,
|
|
.display.has_hotplug = 1,
|
|
.is_lp = 1,
|
|
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
|
|
.has_64bit_reloc = 1,
|
|
.has_runtime_pm = 1,
|
|
.has_rc6 = 1,
|
|
.has_rps = true,
|
|
.has_logical_ring_contexts = 1,
|
|
.display.has_gmch = 1,
|
|
.ppgtt_type = INTEL_PPGTT_FULL,
|
|
.ppgtt_size = 32,
|
|
.has_reset_engine = 1,
|
|
.has_snoop = true,
|
|
.has_coherent_ggtt = false,
|
|
.display_mmio_offset = VLV_DISPLAY_BASE,
|
|
CHV_PIPE_OFFSETS,
|
|
CHV_CURSOR_OFFSETS,
|
|
CHV_COLORS,
|
|
GEN_DEFAULT_PAGE_SIZES,
|
|
};
|
|
|
|
#define GEN9_DEFAULT_PAGE_SIZES \
|
|
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
|
|
I915_GTT_PAGE_SIZE_64K | \
|
|
I915_GTT_PAGE_SIZE_2M
|
|
|
|
#define GEN9_FEATURES \
|
|
GEN8_FEATURES, \
|
|
GEN(9), \
|
|
GEN9_DEFAULT_PAGE_SIZES, \
|
|
.has_logical_ring_preemption = 1, \
|
|
.display.has_csr = 1, \
|
|
.has_guc = 1, \
|
|
.display.has_ipc = 1, \
|
|
.ddb_size = 896
|
|
|
|
#define SKL_PLATFORM \
|
|
GEN9_FEATURES, \
|
|
PLATFORM(INTEL_SKYLAKE)
|
|
|
|
static const struct intel_device_info intel_skylake_gt1_info = {
|
|
SKL_PLATFORM,
|
|
.gt = 1,
|
|
};
|
|
|
|
static const struct intel_device_info intel_skylake_gt2_info = {
|
|
SKL_PLATFORM,
|
|
.gt = 2,
|
|
};
|
|
|
|
#define SKL_GT3_PLUS_PLATFORM \
|
|
SKL_PLATFORM, \
|
|
.engine_mask = \
|
|
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
|
|
|
|
|
|
static const struct intel_device_info intel_skylake_gt3_info = {
|
|
SKL_GT3_PLUS_PLATFORM,
|
|
.gt = 3,
|
|
};
|
|
|
|
static const struct intel_device_info intel_skylake_gt4_info = {
|
|
SKL_GT3_PLUS_PLATFORM,
|
|
.gt = 4,
|
|
};
|
|
|
|
#define GEN9_LP_FEATURES \
|
|
GEN(9), \
|
|
.is_lp = 1, \
|
|
.display.has_hotplug = 1, \
|
|
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
|
|
.num_pipes = 3, \
|
|
.has_64bit_reloc = 1, \
|
|
.display.has_ddi = 1, \
|
|
.has_fpga_dbg = 1, \
|
|
.display.has_fbc = 1, \
|
|
.display.has_psr = 1, \
|
|
.has_runtime_pm = 1, \
|
|
.display.has_csr = 1, \
|
|
.has_rc6 = 1, \
|
|
.has_rps = true, \
|
|
.display.has_dp_mst = 1, \
|
|
.has_logical_ring_contexts = 1, \
|
|
.has_logical_ring_preemption = 1, \
|
|
.has_guc = 1, \
|
|
.ppgtt_type = INTEL_PPGTT_FULL, \
|
|
.ppgtt_size = 48, \
|
|
.has_reset_engine = 1, \
|
|
.has_snoop = true, \
|
|
.has_coherent_ggtt = false, \
|
|
.display.has_ipc = 1, \
|
|
HSW_PIPE_OFFSETS, \
|
|
IVB_CURSOR_OFFSETS, \
|
|
IVB_COLORS, \
|
|
GEN9_DEFAULT_PAGE_SIZES
|
|
|
|
static const struct intel_device_info intel_broxton_info = {
|
|
GEN9_LP_FEATURES,
|
|
PLATFORM(INTEL_BROXTON),
|
|
.ddb_size = 512,
|
|
};
|
|
|
|
static const struct intel_device_info intel_geminilake_info = {
|
|
GEN9_LP_FEATURES,
|
|
PLATFORM(INTEL_GEMINILAKE),
|
|
.ddb_size = 1024,
|
|
GLK_COLORS,
|
|
};
|
|
|
|
#define KBL_PLATFORM \
|
|
GEN9_FEATURES, \
|
|
PLATFORM(INTEL_KABYLAKE)
|
|
|
|
static const struct intel_device_info intel_kabylake_gt1_info = {
|
|
KBL_PLATFORM,
|
|
.gt = 1,
|
|
};
|
|
|
|
static const struct intel_device_info intel_kabylake_gt2_info = {
|
|
KBL_PLATFORM,
|
|
.gt = 2,
|
|
};
|
|
|
|
static const struct intel_device_info intel_kabylake_gt3_info = {
|
|
KBL_PLATFORM,
|
|
.gt = 3,
|
|
.engine_mask =
|
|
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
|
|
};
|
|
|
|
#define CFL_PLATFORM \
|
|
GEN9_FEATURES, \
|
|
PLATFORM(INTEL_COFFEELAKE)
|
|
|
|
static const struct intel_device_info intel_coffeelake_gt1_info = {
|
|
CFL_PLATFORM,
|
|
.gt = 1,
|
|
};
|
|
|
|
static const struct intel_device_info intel_coffeelake_gt2_info = {
|
|
CFL_PLATFORM,
|
|
.gt = 2,
|
|
};
|
|
|
|
static const struct intel_device_info intel_coffeelake_gt3_info = {
|
|
CFL_PLATFORM,
|
|
.gt = 3,
|
|
.engine_mask =
|
|
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
|
|
};
|
|
|
|
#define GEN10_FEATURES \
|
|
GEN9_FEATURES, \
|
|
GEN(10), \
|
|
.ddb_size = 1024, \
|
|
.has_coherent_ggtt = false, \
|
|
GLK_COLORS
|
|
|
|
static const struct intel_device_info intel_cannonlake_info = {
|
|
GEN10_FEATURES,
|
|
PLATFORM(INTEL_CANNONLAKE),
|
|
.gt = 2,
|
|
};
|
|
|
|
#define GEN11_FEATURES \
|
|
GEN10_FEATURES, \
|
|
.pipe_offsets = { \
|
|
[TRANSCODER_A] = PIPE_A_OFFSET, \
|
|
[TRANSCODER_B] = PIPE_B_OFFSET, \
|
|
[TRANSCODER_C] = PIPE_C_OFFSET, \
|
|
[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
|
|
[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
|
|
[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
|
|
}, \
|
|
.trans_offsets = { \
|
|
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
|
|
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
|
|
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
|
|
[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
|
|
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
|
|
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
|
|
}, \
|
|
GEN(11), \
|
|
.ddb_size = 2048, \
|
|
.has_logical_ring_elsq = 1, \
|
|
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
|
|
|
|
static const struct intel_device_info intel_icelake_11_info = {
|
|
GEN11_FEATURES,
|
|
PLATFORM(INTEL_ICELAKE),
|
|
.engine_mask =
|
|
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
|
|
};
|
|
|
|
static const struct intel_device_info intel_elkhartlake_info = {
|
|
GEN11_FEATURES,
|
|
PLATFORM(INTEL_ELKHARTLAKE),
|
|
.require_force_probe = 1,
|
|
.engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
|
|
.ppgtt_size = 36,
|
|
};
|
|
|
|
#undef GEN
|
|
#undef PLATFORM
|
|
|
|
/*
|
|
* Make sure any device matches here are from most specific to most
|
|
* general. For example, since the Quanta match is based on the subsystem
|
|
* and subvendor IDs, we need it to come before the more general IVB
|
|
* PCI ID matches, otherwise we'll use the wrong info struct above.
|
|
*/
|
|
static const struct pci_device_id pciidlist[] = {
|
|
INTEL_I830_IDS(&intel_i830_info),
|
|
INTEL_I845G_IDS(&intel_i845g_info),
|
|
INTEL_I85X_IDS(&intel_i85x_info),
|
|
INTEL_I865G_IDS(&intel_i865g_info),
|
|
INTEL_I915G_IDS(&intel_i915g_info),
|
|
INTEL_I915GM_IDS(&intel_i915gm_info),
|
|
INTEL_I945G_IDS(&intel_i945g_info),
|
|
INTEL_I945GM_IDS(&intel_i945gm_info),
|
|
INTEL_I965G_IDS(&intel_i965g_info),
|
|
INTEL_G33_IDS(&intel_g33_info),
|
|
INTEL_I965GM_IDS(&intel_i965gm_info),
|
|
INTEL_GM45_IDS(&intel_gm45_info),
|
|
INTEL_G45_IDS(&intel_g45_info),
|
|
INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info),
|
|
INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info),
|
|
INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
|
|
INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
|
|
INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
|
|
INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
|
|
INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
|
|
INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
|
|
INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
|
|
INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
|
|
INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
|
|
INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
|
|
INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
|
|
INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
|
|
INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
|
|
INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
|
|
INTEL_VLV_IDS(&intel_valleyview_info),
|
|
INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
|
|
INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
|
|
INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
|
|
INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
|
|
INTEL_CHV_IDS(&intel_cherryview_info),
|
|
INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
|
|
INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
|
|
INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
|
|
INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
|
|
INTEL_BXT_IDS(&intel_broxton_info),
|
|
INTEL_GLK_IDS(&intel_geminilake_info),
|
|
INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
|
|
INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
|
|
INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
|
|
INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
|
|
INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
|
|
INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
|
|
INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
|
|
INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
|
|
INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
|
|
INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
|
|
INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
|
|
INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
|
|
INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
|
|
INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
|
|
INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
|
|
INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
|
|
INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
|
|
INTEL_CNL_IDS(&intel_cannonlake_info),
|
|
INTEL_ICL_11_IDS(&intel_icelake_11_info),
|
|
INTEL_EHL_IDS(&intel_elkhartlake_info),
|
|
{0, 0, 0}
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, pciidlist);
|
|
|
|
static void i915_pci_remove(struct pci_dev *pdev)
|
|
{
|
|
struct drm_device *dev;
|
|
|
|
dev = pci_get_drvdata(pdev);
|
|
if (!dev) /* driver load aborted, nothing to cleanup */
|
|
return;
|
|
|
|
i915_driver_unload(dev);
|
|
drm_dev_put(dev);
|
|
|
|
pci_set_drvdata(pdev, NULL);
|
|
}
|
|
|
|
/* is device_id present in comma separated list of ids */
|
|
static bool force_probe(u16 device_id, const char *devices)
|
|
{
|
|
char *s, *p, *tok;
|
|
bool ret;
|
|
|
|
/* FIXME: transitional */
|
|
if (i915_modparams.alpha_support) {
|
|
DRM_INFO("i915.alpha_support is deprecated, use i915.force_probe=%04x instead\n",
|
|
device_id);
|
|
return true;
|
|
}
|
|
|
|
if (!devices || !*devices)
|
|
return false;
|
|
|
|
/* match everything */
|
|
if (strcmp(devices, "*") == 0)
|
|
return true;
|
|
|
|
s = kstrdup(devices, GFP_KERNEL);
|
|
if (!s)
|
|
return false;
|
|
|
|
for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
|
|
u16 val;
|
|
|
|
if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
|
|
ret = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
kfree(s);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
struct intel_device_info *intel_info =
|
|
(struct intel_device_info *) ent->driver_data;
|
|
int err;
|
|
|
|
if (intel_info->require_force_probe &&
|
|
!force_probe(pdev->device, i915_modparams.force_probe)) {
|
|
DRM_INFO("Your graphics device %04x is not properly supported by the driver in this\n"
|
|
"kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
|
|
"module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
|
|
"or (recommended) check for kernel updates.\n",
|
|
pdev->device, pdev->device, pdev->device);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Only bind to function 0 of the device. Early generations
|
|
* used function 1 as a placeholder for multi-head. This causes
|
|
* us confusion instead, especially on the systems where both
|
|
* functions have the same PCI-ID!
|
|
*/
|
|
if (PCI_FUNC(pdev->devfn))
|
|
return -ENODEV;
|
|
|
|
/*
|
|
* apple-gmux is needed on dual GPU MacBook Pro
|
|
* to probe the panel if we're the inactive GPU.
|
|
*/
|
|
if (vga_switcheroo_client_probe_defer(pdev))
|
|
return -EPROBE_DEFER;
|
|
|
|
err = i915_driver_load(pdev, ent);
|
|
if (err)
|
|
return err;
|
|
|
|
if (i915_inject_load_failure()) {
|
|
i915_pci_remove(pdev);
|
|
return -ENODEV;
|
|
}
|
|
|
|
err = i915_live_selftests(pdev);
|
|
if (err) {
|
|
i915_pci_remove(pdev);
|
|
return err > 0 ? -ENOTTY : err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct pci_driver i915_pci_driver = {
|
|
.name = DRIVER_NAME,
|
|
.id_table = pciidlist,
|
|
.probe = i915_pci_probe,
|
|
.remove = i915_pci_remove,
|
|
.driver.pm = &i915_pm_ops,
|
|
};
|
|
|
|
static int __init i915_init(void)
|
|
{
|
|
bool use_kms = true;
|
|
int err;
|
|
|
|
err = i915_globals_init();
|
|
if (err)
|
|
return err;
|
|
|
|
err = i915_mock_selftests();
|
|
if (err)
|
|
return err > 0 ? 0 : err;
|
|
|
|
/*
|
|
* Enable KMS by default, unless explicitly overriden by
|
|
* either the i915.modeset prarameter or by the
|
|
* vga_text_mode_force boot option.
|
|
*/
|
|
|
|
if (i915_modparams.modeset == 0)
|
|
use_kms = false;
|
|
|
|
if (vgacon_text_force() && i915_modparams.modeset == -1)
|
|
use_kms = false;
|
|
|
|
if (!use_kms) {
|
|
/* Silently fail loading to not upset userspace. */
|
|
DRM_DEBUG_DRIVER("KMS disabled.\n");
|
|
return 0;
|
|
}
|
|
|
|
return pci_register_driver(&i915_pci_driver);
|
|
}
|
|
|
|
static void __exit i915_exit(void)
|
|
{
|
|
if (!i915_pci_driver.driver.owner)
|
|
return;
|
|
|
|
pci_unregister_driver(&i915_pci_driver);
|
|
i915_globals_exit();
|
|
}
|
|
|
|
module_init(i915_init);
|
|
module_exit(i915_exit);
|
|
|
|
MODULE_AUTHOR("Tungsten Graphics, Inc.");
|
|
MODULE_AUTHOR("Intel Corporation");
|
|
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
MODULE_LICENSE("GPL and additional rights");
|