349 lines
14 KiB
Plaintext
349 lines
14 KiB
Plaintext
The x86 kvm shadow mmu
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======================
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The mmu (in arch/x86/kvm, files mmu.[ch] and paging_tmpl.h) is responsible
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for presenting a standard x86 mmu to the guest, while translating guest
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physical addresses to host physical addresses.
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The mmu code attempts to satisfy the following requirements:
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- correctness: the guest should not be able to determine that it is running
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on an emulated mmu except for timing (we attempt to comply
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with the specification, not emulate the characteristics of
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a particular implementation such as tlb size)
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- security: the guest must not be able to touch host memory not assigned
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to it
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- performance: minimize the performance penalty imposed by the mmu
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- scaling: need to scale to large memory and large vcpu guests
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- hardware: support the full range of x86 virtualization hardware
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- integration: Linux memory management code must be in control of guest memory
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so that swapping, page migration, page merging, transparent
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hugepages, and similar features work without change
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- dirty tracking: report writes to guest memory to enable live migration
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and framebuffer-based displays
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- footprint: keep the amount of pinned kernel memory low (most memory
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should be shrinkable)
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- reliablity: avoid multipage or GFP_ATOMIC allocations
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Acronyms
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========
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pfn host page frame number
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hpa host physical address
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hva host virtual address
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gfn guest frame number
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gpa guest physical address
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gva guest virtual address
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ngpa nested guest physical address
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ngva nested guest virtual address
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pte page table entry (used also to refer generically to paging structure
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entries)
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gpte guest pte (referring to gfns)
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spte shadow pte (referring to pfns)
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tdp two dimensional paging (vendor neutral term for NPT and EPT)
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Virtual and real hardware supported
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===================================
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The mmu supports first-generation mmu hardware, which allows an atomic switch
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of the current paging mode and cr3 during guest entry, as well as
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two-dimensional paging (AMD's NPT and Intel's EPT). The emulated hardware
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it exposes is the traditional 2/3/4 level x86 mmu, with support for global
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pages, pae, pse, pse36, cr0.wp, and 1GB pages. Work is in progress to support
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exposing NPT capable hardware on NPT capable hosts.
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Translation
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===========
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The primary job of the mmu is to program the processor's mmu to translate
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addresses for the guest. Different translations are required at different
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times:
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- when guest paging is disabled, we translate guest physical addresses to
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host physical addresses (gpa->hpa)
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- when guest paging is enabled, we translate guest virtual addresses, to
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guest physical addresses, to host physical addresses (gva->gpa->hpa)
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- when the guest launches a guest of its own, we translate nested guest
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virtual addresses, to nested guest physical addresses, to guest physical
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addresses, to host physical addresses (ngva->ngpa->gpa->hpa)
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The primary challenge is to encode between 1 and 3 translations into hardware
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that support only 1 (traditional) and 2 (tdp) translations. When the
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number of required translations matches the hardware, the mmu operates in
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direct mode; otherwise it operates in shadow mode (see below).
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Memory
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======
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Guest memory (gpa) is part of the user address space of the process that is
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using kvm. Userspace defines the translation between guest addresses and user
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addresses (gpa->hva); note that two gpas may alias to the same hva, but not
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vice versa.
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These hvas may be backed using any method available to the host: anonymous
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memory, file backed memory, and device memory. Memory might be paged by the
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host at any time.
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Events
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======
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The mmu is driven by events, some from the guest, some from the host.
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Guest generated events:
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- writes to control registers (especially cr3)
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- invlpg/invlpga instruction execution
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- access to missing or protected translations
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Host generated events:
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- changes in the gpa->hpa translation (either through gpa->hva changes or
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through hva->hpa changes)
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- memory pressure (the shrinker)
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Shadow pages
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============
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The principal data structure is the shadow page, 'struct kvm_mmu_page'. A
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shadow page contains 512 sptes, which can be either leaf or nonleaf sptes. A
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shadow page may contain a mix of leaf and nonleaf sptes.
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A nonleaf spte allows the hardware mmu to reach the leaf pages and
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is not related to a translation directly. It points to other shadow pages.
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A leaf spte corresponds to either one or two translations encoded into
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one paging structure entry. These are always the lowest level of the
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translation stack, with optional higher level translations left to NPT/EPT.
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Leaf ptes point at guest pages.
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The following table shows translations encoded by leaf ptes, with higher-level
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translations in parentheses:
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Non-nested guests:
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nonpaging: gpa->hpa
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paging: gva->gpa->hpa
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paging, tdp: (gva->)gpa->hpa
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Nested guests:
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non-tdp: ngva->gpa->hpa (*)
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tdp: (ngva->)ngpa->gpa->hpa
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(*) the guest hypervisor will encode the ngva->gpa translation into its page
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tables if npt is not present
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Shadow pages contain the following information:
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role.level:
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The level in the shadow paging hierarchy that this shadow page belongs to.
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1=4k sptes, 2=2M sptes, 3=1G sptes, etc.
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role.direct:
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If set, leaf sptes reachable from this page are for a linear range.
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Examples include real mode translation, large guest pages backed by small
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host pages, and gpa->hpa translations when NPT or EPT is active.
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The linear range starts at (gfn << PAGE_SHIFT) and its size is determined
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by role.level (2MB for first level, 1GB for second level, 0.5TB for third
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level, 256TB for fourth level)
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If clear, this page corresponds to a guest page table denoted by the gfn
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field.
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role.quadrant:
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When role.cr4_pae=0, the guest uses 32-bit gptes while the host uses 64-bit
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sptes. That means a guest page table contains more ptes than the host,
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so multiple shadow pages are needed to shadow one guest page.
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For first-level shadow pages, role.quadrant can be 0 or 1 and denotes the
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first or second 512-gpte block in the guest page table. For second-level
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page tables, each 32-bit gpte is converted to two 64-bit sptes
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(since each first-level guest page is shadowed by two first-level
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shadow pages) so role.quadrant takes values in the range 0..3. Each
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quadrant maps 1GB virtual address space.
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role.access:
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Inherited guest access permissions in the form uwx. Note execute
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permission is positive, not negative.
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role.invalid:
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The page is invalid and should not be used. It is a root page that is
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currently pinned (by a cpu hardware register pointing to it); once it is
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unpinned it will be destroyed.
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role.cr4_pae:
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Contains the value of cr4.pae for which the page is valid (e.g. whether
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32-bit or 64-bit gptes are in use).
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role.nxe:
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Contains the value of efer.nxe for which the page is valid.
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role.cr0_wp:
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Contains the value of cr0.wp for which the page is valid.
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gfn:
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Either the guest page table containing the translations shadowed by this
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page, or the base page frame for linear translations. See role.direct.
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spt:
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A pageful of 64-bit sptes containing the translations for this page.
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Accessed by both kvm and hardware.
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The page pointed to by spt will have its page->private pointing back
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at the shadow page structure.
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sptes in spt point either at guest pages, or at lower-level shadow pages.
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Specifically, if sp1 and sp2 are shadow pages, then sp1->spt[n] may point
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at __pa(sp2->spt). sp2 will point back at sp1 through parent_pte.
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The spt array forms a DAG structure with the shadow page as a node, and
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guest pages as leaves.
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gfns:
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An array of 512 guest frame numbers, one for each present pte. Used to
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perform a reverse map from a pte to a gfn. When role.direct is set, any
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element of this array can be calculated from the gfn field when used, in
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this case, the array of gfns is not allocated. See role.direct and gfn.
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slot_bitmap:
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A bitmap containing one bit per memory slot. If the page contains a pte
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mapping a page from memory slot n, then bit n of slot_bitmap will be set
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(if a page is aliased among several slots, then it is not guaranteed that
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all slots will be marked).
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Used during dirty logging to avoid scanning a shadow page if none if its
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pages need tracking.
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root_count:
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A counter keeping track of how many hardware registers (guest cr3 or
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pdptrs) are now pointing at the page. While this counter is nonzero, the
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page cannot be destroyed. See role.invalid.
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multimapped:
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Whether there exist multiple sptes pointing at this page.
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parent_pte/parent_ptes:
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If multimapped is zero, parent_pte points at the single spte that points at
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this page's spt. Otherwise, parent_ptes points at a data structure
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with a list of parent_ptes.
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unsync:
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If true, then the translations in this page may not match the guest's
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translation. This is equivalent to the state of the tlb when a pte is
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changed but before the tlb entry is flushed. Accordingly, unsync ptes
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are synchronized when the guest executes invlpg or flushes its tlb by
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other means. Valid for leaf pages.
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unsync_children:
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How many sptes in the page point at pages that are unsync (or have
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unsynchronized children).
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unsync_child_bitmap:
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A bitmap indicating which sptes in spt point (directly or indirectly) at
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pages that may be unsynchronized. Used to quickly locate all unsychronized
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pages reachable from a given page.
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Reverse map
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===========
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The mmu maintains a reverse mapping whereby all ptes mapping a page can be
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reached given its gfn. This is used, for example, when swapping out a page.
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Synchronized and unsynchronized pages
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=====================================
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The guest uses two events to synchronize its tlb and page tables: tlb flushes
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and page invalidations (invlpg).
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A tlb flush means that we need to synchronize all sptes reachable from the
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guest's cr3. This is expensive, so we keep all guest page tables write
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protected, and synchronize sptes to gptes when a gpte is written.
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A special case is when a guest page table is reachable from the current
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guest cr3. In this case, the guest is obliged to issue an invlpg instruction
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before using the translation. We take advantage of that by removing write
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protection from the guest page, and allowing the guest to modify it freely.
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We synchronize modified gptes when the guest invokes invlpg. This reduces
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the amount of emulation we have to do when the guest modifies multiple gptes,
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or when the a guest page is no longer used as a page table and is used for
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random guest data.
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As a side effect we have to resynchronize all reachable unsynchronized shadow
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pages on a tlb flush.
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Reaction to events
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==================
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- guest page fault (or npt page fault, or ept violation)
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This is the most complicated event. The cause of a page fault can be:
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- a true guest fault (the guest translation won't allow the access) (*)
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- access to a missing translation
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- access to a protected translation
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- when logging dirty pages, memory is write protected
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- synchronized shadow pages are write protected (*)
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- access to untranslatable memory (mmio)
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(*) not applicable in direct mode
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Handling a page fault is performed as follows:
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- if needed, walk the guest page tables to determine the guest translation
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(gva->gpa or ngpa->gpa)
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- if permissions are insufficient, reflect the fault back to the guest
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- determine the host page
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- if this is an mmio request, there is no host page; call the emulator
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to emulate the instruction instead
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- walk the shadow page table to find the spte for the translation,
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instantiating missing intermediate page tables as necessary
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- try to unsynchronize the page
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- if successful, we can let the guest continue and modify the gpte
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- emulate the instruction
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- if failed, unshadow the page and let the guest continue
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- update any translations that were modified by the instruction
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invlpg handling:
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- walk the shadow page hierarchy and drop affected translations
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- try to reinstantiate the indicated translation in the hope that the
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guest will use it in the near future
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Guest control register updates:
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- mov to cr3
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- look up new shadow roots
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- synchronize newly reachable shadow pages
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- mov to cr0/cr4/efer
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- set up mmu context for new paging mode
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- look up new shadow roots
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- synchronize newly reachable shadow pages
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Host translation updates:
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- mmu notifier called with updated hva
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- look up affected sptes through reverse map
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- drop (or update) translations
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Emulating cr0.wp
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================
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If tdp is not enabled, the host must keep cr0.wp=1 so page write protection
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works for the guest kernel, not guest guest userspace. When the guest
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cr0.wp=1, this does not present a problem. However when the guest cr0.wp=0,
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we cannot map the permissions for gpte.u=1, gpte.w=0 to any spte (the
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semantics require allowing any guest kernel access plus user read access).
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We handle this by mapping the permissions to two possible sptes, depending
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on fault type:
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- kernel write fault: spte.u=0, spte.w=1 (allows full kernel access,
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disallows user access)
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- read fault: spte.u=1, spte.w=0 (allows full read access, disallows kernel
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write access)
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(user write faults generate a #PF)
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Large pages
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===========
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The mmu supports all combinations of large and small guest and host pages.
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Supported page sizes include 4k, 2M, 4M, and 1G. 4M pages are treated as
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two separate 2M pages, on both guest and host, since the mmu always uses PAE
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paging.
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To instantiate a large spte, four constraints must be satisfied:
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- the spte must point to a large host page
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- the guest pte must be a large pte of at least equivalent size (if tdp is
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enabled, there is no guest pte and this condition is satisified)
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- if the spte will be writeable, the large page frame may not overlap any
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write-protected pages
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- the guest page must be wholly contained by a single memory slot
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To check the last two conditions, the mmu maintains a ->write_count set of
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arrays for each memory slot and large page size. Every write protected page
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causes its write_count to be incremented, thus preventing instantiation of
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a large spte. The frames at the end of an unaligned memory slot have
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artificically inflated ->write_counts so they can never be instantiated.
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Further reading
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===============
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- NPT presentation from KVM Forum 2008
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http://www.linux-kvm.org/wiki/images/c/c8/KvmForum2008%24kdf2008_21.pdf
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