388 lines
12 KiB
C
388 lines
12 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <drm/drm_print.h>
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#include <drm/i915_pciids.h>
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#include "display/intel_cdclk.h"
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#include "display/intel_de.h"
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#include "intel_device_info.h"
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#include "i915_drv.h"
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#define PLATFORM_NAME(x) [INTEL_##x] = #x
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static const char * const platform_names[] = {
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PLATFORM_NAME(I830),
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PLATFORM_NAME(I845G),
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PLATFORM_NAME(I85X),
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PLATFORM_NAME(I865G),
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PLATFORM_NAME(I915G),
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PLATFORM_NAME(I915GM),
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PLATFORM_NAME(I945G),
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PLATFORM_NAME(I945GM),
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PLATFORM_NAME(G33),
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PLATFORM_NAME(PINEVIEW),
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PLATFORM_NAME(I965G),
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PLATFORM_NAME(I965GM),
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PLATFORM_NAME(G45),
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PLATFORM_NAME(GM45),
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PLATFORM_NAME(IRONLAKE),
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PLATFORM_NAME(SANDYBRIDGE),
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PLATFORM_NAME(IVYBRIDGE),
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PLATFORM_NAME(VALLEYVIEW),
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PLATFORM_NAME(HASWELL),
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PLATFORM_NAME(BROADWELL),
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PLATFORM_NAME(CHERRYVIEW),
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PLATFORM_NAME(SKYLAKE),
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PLATFORM_NAME(BROXTON),
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PLATFORM_NAME(KABYLAKE),
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PLATFORM_NAME(GEMINILAKE),
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PLATFORM_NAME(COFFEELAKE),
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PLATFORM_NAME(COMETLAKE),
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PLATFORM_NAME(CANNONLAKE),
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PLATFORM_NAME(ICELAKE),
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PLATFORM_NAME(ELKHARTLAKE),
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PLATFORM_NAME(JASPERLAKE),
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PLATFORM_NAME(TIGERLAKE),
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PLATFORM_NAME(ROCKETLAKE),
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PLATFORM_NAME(DG1),
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PLATFORM_NAME(ALDERLAKE_S),
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PLATFORM_NAME(ALDERLAKE_P),
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};
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#undef PLATFORM_NAME
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const char *intel_platform_name(enum intel_platform platform)
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{
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BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
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if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
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platform_names[platform] == NULL))
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return "<unknown>";
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return platform_names[platform];
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}
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static const char *iommu_name(void)
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{
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const char *msg = "n/a";
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#ifdef CONFIG_INTEL_IOMMU
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msg = enableddisabled(intel_iommu_gfx_mapped);
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#endif
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return msg;
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}
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void intel_device_info_print_static(const struct intel_device_info *info,
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struct drm_printer *p)
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{
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drm_printf(p, "graphics_ver: %u\n", info->graphics_ver);
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drm_printf(p, "media_ver: %u\n", info->media_ver);
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drm_printf(p, "display_ver: %u\n", info->display.ver);
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drm_printf(p, "gt: %d\n", info->gt);
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drm_printf(p, "iommu: %s\n", iommu_name());
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drm_printf(p, "memory-regions: %x\n", info->memory_regions);
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drm_printf(p, "page-sizes: %x\n", info->page_sizes);
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drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
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drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
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drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
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drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
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#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name))
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DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
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#undef PRINT_FLAG
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#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
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DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
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#undef PRINT_FLAG
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}
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void intel_device_info_print_runtime(const struct intel_runtime_info *info,
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struct drm_printer *p)
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{
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drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
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}
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#undef INTEL_VGA_DEVICE
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#define INTEL_VGA_DEVICE(id, info) (id)
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static const u16 subplatform_ult_ids[] = {
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INTEL_HSW_ULT_GT1_IDS(0),
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INTEL_HSW_ULT_GT2_IDS(0),
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INTEL_HSW_ULT_GT3_IDS(0),
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INTEL_BDW_ULT_GT1_IDS(0),
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INTEL_BDW_ULT_GT2_IDS(0),
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INTEL_BDW_ULT_GT3_IDS(0),
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INTEL_BDW_ULT_RSVD_IDS(0),
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INTEL_SKL_ULT_GT1_IDS(0),
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INTEL_SKL_ULT_GT2_IDS(0),
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INTEL_SKL_ULT_GT3_IDS(0),
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INTEL_KBL_ULT_GT1_IDS(0),
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INTEL_KBL_ULT_GT2_IDS(0),
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INTEL_KBL_ULT_GT3_IDS(0),
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INTEL_CFL_U_GT2_IDS(0),
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INTEL_CFL_U_GT3_IDS(0),
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INTEL_WHL_U_GT1_IDS(0),
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INTEL_WHL_U_GT2_IDS(0),
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INTEL_WHL_U_GT3_IDS(0),
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INTEL_CML_U_GT1_IDS(0),
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INTEL_CML_U_GT2_IDS(0),
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};
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static const u16 subplatform_ulx_ids[] = {
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INTEL_HSW_ULX_GT1_IDS(0),
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INTEL_HSW_ULX_GT2_IDS(0),
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INTEL_BDW_ULX_GT1_IDS(0),
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INTEL_BDW_ULX_GT2_IDS(0),
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INTEL_BDW_ULX_GT3_IDS(0),
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INTEL_BDW_ULX_RSVD_IDS(0),
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INTEL_SKL_ULX_GT1_IDS(0),
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INTEL_SKL_ULX_GT2_IDS(0),
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INTEL_KBL_ULX_GT1_IDS(0),
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INTEL_KBL_ULX_GT2_IDS(0),
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INTEL_AML_KBL_GT2_IDS(0),
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INTEL_AML_CFL_GT2_IDS(0),
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};
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static const u16 subplatform_portf_ids[] = {
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INTEL_CNL_PORT_F_IDS(0),
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INTEL_ICL_PORT_F_IDS(0),
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};
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static bool find_devid(u16 id, const u16 *p, unsigned int num)
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{
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for (; num; num--, p++) {
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if (*p == id)
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return true;
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}
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return false;
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}
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void intel_device_info_subplatform_init(struct drm_i915_private *i915)
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{
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const struct intel_device_info *info = INTEL_INFO(i915);
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const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
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const unsigned int pi = __platform_mask_index(rinfo, info->platform);
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const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
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u16 devid = INTEL_DEVID(i915);
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u32 mask = 0;
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/* Make sure IS_<platform> checks are working. */
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RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
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/* Find and mark subplatform bits based on the PCI device id. */
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if (find_devid(devid, subplatform_ult_ids,
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ARRAY_SIZE(subplatform_ult_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_ULT);
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} else if (find_devid(devid, subplatform_ulx_ids,
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ARRAY_SIZE(subplatform_ulx_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_ULX);
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if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
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/* ULX machines are also considered ULT. */
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mask |= BIT(INTEL_SUBPLATFORM_ULT);
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}
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} else if (find_devid(devid, subplatform_portf_ids,
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ARRAY_SIZE(subplatform_portf_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_PORTF);
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}
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if (IS_TIGERLAKE(i915)) {
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struct pci_dev *root, *pdev = to_pci_dev(i915->drm.dev);
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root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list);
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drm_WARN_ON(&i915->drm, mask);
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drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) !=
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TGL_ROOT_DEVICE_ID);
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switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) {
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case TGL_ROOT_DEVICE_SKU_ULX:
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mask = BIT(INTEL_SUBPLATFORM_ULX);
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break;
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case TGL_ROOT_DEVICE_SKU_ULT:
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mask = BIT(INTEL_SUBPLATFORM_ULT);
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break;
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}
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}
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GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
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RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
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}
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/**
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* intel_device_info_runtime_init - initialize runtime info
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* @dev_priv: the i915 device
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*
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* Determine various intel_device_info fields at runtime.
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*
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* Use it when either:
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* - it's judged too laborious to fill n static structures with the limit
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* when a simple if statement does the job,
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* - run-time checks (eg read fuse/strap registers) are needed.
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*
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* This function needs to be called:
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* - after the MMIO has been setup as we are reading registers,
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* - after the PCH has been detected,
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* - before the first usage of the fields it can tweak.
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*/
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void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
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{
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struct intel_device_info *info = mkwrite_device_info(dev_priv);
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struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
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enum pipe pipe;
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/* Wa_14011765242: adl-s A0 */
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if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
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for_each_pipe(dev_priv, pipe)
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runtime->num_scalers[pipe] = 0;
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else if (GRAPHICS_VER(dev_priv) >= 10) {
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for_each_pipe(dev_priv, pipe)
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runtime->num_scalers[pipe] = 2;
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} else if (GRAPHICS_VER(dev_priv) == 9) {
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runtime->num_scalers[PIPE_A] = 2;
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runtime->num_scalers[PIPE_B] = 2;
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runtime->num_scalers[PIPE_C] = 1;
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}
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BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
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if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
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for_each_pipe(dev_priv, pipe)
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runtime->num_sprites[pipe] = 4;
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else if (GRAPHICS_VER(dev_priv) >= 11)
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for_each_pipe(dev_priv, pipe)
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runtime->num_sprites[pipe] = 6;
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else if (GRAPHICS_VER(dev_priv) == 10 || IS_GEMINILAKE(dev_priv))
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for_each_pipe(dev_priv, pipe)
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runtime->num_sprites[pipe] = 3;
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else if (IS_BROXTON(dev_priv)) {
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/*
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* Skylake and Broxton currently don't expose the topmost plane as its
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* use is exclusive with the legacy cursor and we only want to expose
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* one of those, not both. Until we can safely expose the topmost plane
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* as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
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* we don't expose the topmost plane at all to prevent ABI breakage
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* down the line.
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*/
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runtime->num_sprites[PIPE_A] = 2;
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runtime->num_sprites[PIPE_B] = 2;
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runtime->num_sprites[PIPE_C] = 1;
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} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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for_each_pipe(dev_priv, pipe)
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runtime->num_sprites[pipe] = 2;
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} else if (GRAPHICS_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
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for_each_pipe(dev_priv, pipe)
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runtime->num_sprites[pipe] = 1;
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}
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if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
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HAS_PCH_SPLIT(dev_priv)) {
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u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
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u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
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/*
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* SFUSE_STRAP is supposed to have a bit signalling the display
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* is fused off. Unfortunately it seems that, at least in
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* certain cases, fused off display means that PCH display
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* reads don't land anywhere. In that case, we read 0s.
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*
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* On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
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* should be set when taking over after the firmware.
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*/
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if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
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sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
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(HAS_PCH_CPT(dev_priv) &&
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!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
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drm_info(&dev_priv->drm,
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"Display fused off, disabling\n");
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info->pipe_mask = 0;
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info->cpu_transcoder_mask = 0;
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} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
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drm_info(&dev_priv->drm, "PipeC fused off\n");
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info->pipe_mask &= ~BIT(PIPE_C);
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info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
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}
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} else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) {
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u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
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if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
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info->pipe_mask &= ~BIT(PIPE_A);
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info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
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}
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if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
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info->pipe_mask &= ~BIT(PIPE_B);
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info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
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}
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if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
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info->pipe_mask &= ~BIT(PIPE_C);
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info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
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}
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if (GRAPHICS_VER(dev_priv) >= 12 &&
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(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
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info->pipe_mask &= ~BIT(PIPE_D);
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info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
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}
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if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
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info->display.has_hdcp = 0;
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if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
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info->display.has_fbc = 0;
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if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
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info->display.has_dmc = 0;
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if (GRAPHICS_VER(dev_priv) >= 10 &&
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(dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
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info->display.has_dsc = 0;
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}
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if (GRAPHICS_VER(dev_priv) == 6 && intel_vtd_active()) {
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drm_info(&dev_priv->drm,
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"Disabling ppGTT for VT-d support\n");
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info->ppgtt_type = INTEL_PPGTT_NONE;
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}
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runtime->rawclk_freq = intel_read_rawclk(dev_priv);
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drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
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if (!HAS_DISPLAY(dev_priv)) {
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dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
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DRIVER_ATOMIC);
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memset(&info->display, 0, sizeof(info->display));
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memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
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memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
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}
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}
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void intel_driver_caps_print(const struct intel_driver_caps *caps,
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struct drm_printer *p)
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{
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drm_printf(p, "Has logical contexts? %s\n",
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yesno(caps->has_logical_contexts));
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drm_printf(p, "scheduler: %x\n", caps->scheduler);
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}
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