142 lines
4.0 KiB
C
142 lines
4.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef INTEL_RING_H
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#define INTEL_RING_H
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#include "i915_gem.h" /* GEM_BUG_ON */
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#include "i915_request.h"
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#include "intel_ring_types.h"
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struct intel_engine_cs;
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struct intel_ring *
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intel_engine_create_ring(struct intel_engine_cs *engine, int size);
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u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords);
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int intel_ring_cacheline_align(struct i915_request *rq);
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unsigned int intel_ring_update_space(struct intel_ring *ring);
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void __intel_ring_pin(struct intel_ring *ring);
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int intel_ring_pin(struct intel_ring *ring, struct i915_gem_ww_ctx *ww);
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void intel_ring_unpin(struct intel_ring *ring);
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void intel_ring_reset(struct intel_ring *ring, u32 tail);
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void intel_ring_free(struct kref *ref);
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static inline struct intel_ring *intel_ring_get(struct intel_ring *ring)
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{
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kref_get(&ring->ref);
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return ring;
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}
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static inline void intel_ring_put(struct intel_ring *ring)
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{
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kref_put(&ring->ref, intel_ring_free);
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}
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static inline void intel_ring_advance(struct i915_request *rq, u32 *cs)
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{
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/* Dummy function.
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*
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* This serves as a placeholder in the code so that the reader
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* can compare against the preceding intel_ring_begin() and
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* check that the number of dwords emitted matches the space
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* reserved for the command packet (i.e. the value passed to
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* intel_ring_begin()).
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*/
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GEM_BUG_ON((rq->ring->vaddr + rq->ring->emit) != cs);
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}
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static inline u32 intel_ring_wrap(const struct intel_ring *ring, u32 pos)
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{
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return pos & (ring->size - 1);
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}
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static inline int intel_ring_direction(const struct intel_ring *ring,
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u32 next, u32 prev)
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{
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typecheck(typeof(ring->size), next);
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typecheck(typeof(ring->size), prev);
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return (next - prev) << ring->wrap;
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}
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static inline bool
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intel_ring_offset_valid(const struct intel_ring *ring,
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unsigned int pos)
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{
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if (pos & -ring->size) /* must be strictly within the ring */
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return false;
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if (!IS_ALIGNED(pos, 8)) /* must be qword aligned */
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return false;
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return true;
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}
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static inline u32 intel_ring_offset(const struct i915_request *rq, void *addr)
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{
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/* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
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u32 offset = addr - rq->ring->vaddr;
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GEM_BUG_ON(offset > rq->ring->size);
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return intel_ring_wrap(rq->ring, offset);
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}
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static inline void
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assert_ring_tail_valid(const struct intel_ring *ring, unsigned int tail)
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{
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unsigned int head = READ_ONCE(ring->head);
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GEM_BUG_ON(!intel_ring_offset_valid(ring, tail));
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/*
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* "Ring Buffer Use"
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* Gen2 BSpec "1. Programming Environment" / 1.4.4.6
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* Gen3 BSpec "1c Memory Interface Functions" / 2.3.4.5
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* Gen4+ BSpec "1c Memory Interface and Command Stream" / 5.3.4.5
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* "If the Ring Buffer Head Pointer and the Tail Pointer are on the
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* same cacheline, the Head Pointer must not be greater than the Tail
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* Pointer."
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*
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* We use ring->head as the last known location of the actual RING_HEAD,
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* it may have advanced but in the worst case it is equally the same
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* as ring->head and so we should never program RING_TAIL to advance
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* into the same cacheline as ring->head.
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*/
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#define cacheline(a) round_down(a, CACHELINE_BYTES)
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GEM_BUG_ON(cacheline(tail) == cacheline(head) && tail < head);
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#undef cacheline
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}
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static inline unsigned int
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intel_ring_set_tail(struct intel_ring *ring, unsigned int tail)
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{
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/* Whilst writes to the tail are strictly order, there is no
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* serialisation between readers and the writers. The tail may be
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* read by i915_request_retire() just as it is being updated
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* by execlists, as although the breadcrumb is complete, the context
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* switch hasn't been seen.
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*/
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assert_ring_tail_valid(ring, tail);
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ring->tail = tail;
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return tail;
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}
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static inline unsigned int
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__intel_ring_space(unsigned int head, unsigned int tail, unsigned int size)
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{
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/*
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* "If the Ring Buffer Head Pointer and the Tail Pointer are on the
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* same cacheline, the Head Pointer must not be greater than the Tail
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* Pointer."
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*/
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GEM_BUG_ON(!is_power_of_2(size));
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return (head - tail - CACHELINE_BYTES) & (size - 1);
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}
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#endif /* INTEL_RING_H */
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