631 lines
20 KiB
C
631 lines
20 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include <linux/seq_file.h>
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#include "debugfs_gt.h"
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#include "debugfs_gt_pm.h"
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#include "i915_drv.h"
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#include "intel_gt.h"
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#include "intel_gt_clock_utils.h"
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#include "intel_gt_pm.h"
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#include "intel_llc.h"
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#include "intel_rc6.h"
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#include "intel_rps.h"
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#include "intel_runtime_pm.h"
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#include "intel_sideband.h"
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#include "intel_uncore.h"
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static int fw_domains_show(struct seq_file *m, void *data)
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{
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struct intel_gt *gt = m->private;
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struct intel_uncore *uncore = gt->uncore;
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struct intel_uncore_forcewake_domain *fw_domain;
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unsigned int tmp;
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seq_printf(m, "user.bypass_count = %u\n",
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uncore->user_forcewake_count);
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for_each_fw_domain(fw_domain, uncore, tmp)
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seq_printf(m, "%s.wake_count = %u\n",
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intel_uncore_forcewake_domain_to_str(fw_domain->id),
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READ_ONCE(fw_domain->wake_count));
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return 0;
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}
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DEFINE_GT_DEBUGFS_ATTRIBUTE(fw_domains);
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static void print_rc6_res(struct seq_file *m,
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const char *title,
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const i915_reg_t reg)
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{
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struct intel_gt *gt = m->private;
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intel_wakeref_t wakeref;
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with_intel_runtime_pm(gt->uncore->rpm, wakeref)
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seq_printf(m, "%s %u (%llu us)\n", title,
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intel_uncore_read(gt->uncore, reg),
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intel_rc6_residency_us(>->rc6, reg));
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}
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static int vlv_drpc(struct seq_file *m)
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{
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struct intel_gt *gt = m->private;
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struct intel_uncore *uncore = gt->uncore;
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u32 rcctl1, pw_status;
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pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS);
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rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
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seq_printf(m, "RC6 Enabled: %s\n",
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yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
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GEN6_RC_CTL_EI_MODE(1))));
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seq_printf(m, "Render Power Well: %s\n",
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(pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
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seq_printf(m, "Media Power Well: %s\n",
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(pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
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print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
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print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
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return fw_domains_show(m, NULL);
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}
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static int gen6_drpc(struct seq_file *m)
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{
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struct intel_gt *gt = m->private;
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struct drm_i915_private *i915 = gt->i915;
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struct intel_uncore *uncore = gt->uncore;
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u32 gt_core_status, rcctl1, rc6vids = 0;
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u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
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gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
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rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
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if (GRAPHICS_VER(i915) >= 9) {
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gen9_powergate_enable =
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intel_uncore_read(uncore, GEN9_PG_ENABLE);
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gen9_powergate_status =
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intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
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}
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if (GRAPHICS_VER(i915) <= 7)
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sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
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&rc6vids, NULL);
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seq_printf(m, "RC1e Enabled: %s\n",
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yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
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seq_printf(m, "RC6 Enabled: %s\n",
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yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
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if (GRAPHICS_VER(i915) >= 9) {
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seq_printf(m, "Render Well Gating Enabled: %s\n",
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yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
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seq_printf(m, "Media Well Gating Enabled: %s\n",
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yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
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}
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seq_printf(m, "Deep RC6 Enabled: %s\n",
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yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
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seq_printf(m, "Deepest RC6 Enabled: %s\n",
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yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
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seq_puts(m, "Current RC state: ");
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switch (gt_core_status & GEN6_RCn_MASK) {
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case GEN6_RC0:
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if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
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seq_puts(m, "Core Power Down\n");
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else
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seq_puts(m, "on\n");
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break;
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case GEN6_RC3:
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seq_puts(m, "RC3\n");
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break;
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case GEN6_RC6:
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seq_puts(m, "RC6\n");
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break;
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case GEN6_RC7:
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seq_puts(m, "RC7\n");
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break;
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default:
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seq_puts(m, "Unknown\n");
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break;
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}
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seq_printf(m, "Core Power Down: %s\n",
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yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
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if (GRAPHICS_VER(i915) >= 9) {
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seq_printf(m, "Render Power Well: %s\n",
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(gen9_powergate_status &
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GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
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seq_printf(m, "Media Power Well: %s\n",
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(gen9_powergate_status &
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GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
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}
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/* Not exactly sure what this is */
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print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
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GEN6_GT_GFX_RC6_LOCKED);
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print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
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print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
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print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
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if (GRAPHICS_VER(i915) <= 7) {
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seq_printf(m, "RC6 voltage: %dmV\n",
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GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
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seq_printf(m, "RC6+ voltage: %dmV\n",
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GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
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seq_printf(m, "RC6++ voltage: %dmV\n",
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GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
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}
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return fw_domains_show(m, NULL);
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}
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static int ilk_drpc(struct seq_file *m)
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{
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struct intel_gt *gt = m->private;
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struct intel_uncore *uncore = gt->uncore;
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u32 rgvmodectl, rstdbyctl;
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u16 crstandvid;
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rgvmodectl = intel_uncore_read(uncore, MEMMODECTL);
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rstdbyctl = intel_uncore_read(uncore, RSTDBYCTL);
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crstandvid = intel_uncore_read16(uncore, CRSTANDVID);
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seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
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seq_printf(m, "Boost freq: %d\n",
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(rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
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MEMMODE_BOOST_FREQ_SHIFT);
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seq_printf(m, "HW control enabled: %s\n",
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yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
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seq_printf(m, "SW control enabled: %s\n",
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yesno(rgvmodectl & MEMMODE_SWMODE_EN));
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seq_printf(m, "Gated voltage change: %s\n",
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yesno(rgvmodectl & MEMMODE_RCLK_GATE));
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seq_printf(m, "Starting frequency: P%d\n",
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(rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
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seq_printf(m, "Max P-state: P%d\n",
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(rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
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seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
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seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
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seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
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seq_printf(m, "Render standby enabled: %s\n",
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yesno(!(rstdbyctl & RCX_SW_EXIT)));
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seq_puts(m, "Current RS state: ");
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switch (rstdbyctl & RSX_STATUS_MASK) {
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case RSX_STATUS_ON:
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seq_puts(m, "on\n");
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break;
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case RSX_STATUS_RC1:
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seq_puts(m, "RC1\n");
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break;
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case RSX_STATUS_RC1E:
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seq_puts(m, "RC1E\n");
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break;
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case RSX_STATUS_RS1:
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seq_puts(m, "RS1\n");
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break;
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case RSX_STATUS_RS2:
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seq_puts(m, "RS2 (RC6)\n");
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break;
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case RSX_STATUS_RS3:
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seq_puts(m, "RC3 (RC6+)\n");
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break;
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default:
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seq_puts(m, "unknown\n");
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break;
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}
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return 0;
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}
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static int drpc_show(struct seq_file *m, void *unused)
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{
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struct intel_gt *gt = m->private;
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struct drm_i915_private *i915 = gt->i915;
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intel_wakeref_t wakeref;
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int err = -ENODEV;
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with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
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if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
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err = vlv_drpc(m);
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else if (GRAPHICS_VER(i915) >= 6)
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err = gen6_drpc(m);
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else
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err = ilk_drpc(m);
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}
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return err;
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}
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DEFINE_GT_DEBUGFS_ATTRIBUTE(drpc);
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static int frequency_show(struct seq_file *m, void *unused)
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{
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struct intel_gt *gt = m->private;
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struct drm_i915_private *i915 = gt->i915;
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struct intel_uncore *uncore = gt->uncore;
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struct intel_rps *rps = >->rps;
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intel_wakeref_t wakeref;
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wakeref = intel_runtime_pm_get(uncore->rpm);
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if (GRAPHICS_VER(i915) == 5) {
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u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
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u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
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seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
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seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
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seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
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MEMSTAT_VID_SHIFT);
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seq_printf(m, "Current P-state: %d\n",
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(rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
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} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
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u32 rpmodectl, freq_sts;
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rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
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seq_printf(m, "Video Turbo Mode: %s\n",
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yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
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seq_printf(m, "HW control enabled: %s\n",
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yesno(rpmodectl & GEN6_RP_ENABLE));
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seq_printf(m, "SW control enabled: %s\n",
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yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
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GEN6_RP_MEDIA_SW_MODE));
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vlv_punit_get(i915);
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freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
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vlv_punit_put(i915);
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seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
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seq_printf(m, "DDR freq: %d MHz\n", i915->mem_freq);
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seq_printf(m, "actual GPU freq: %d MHz\n",
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intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
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seq_printf(m, "current GPU freq: %d MHz\n",
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intel_gpu_freq(rps, rps->cur_freq));
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seq_printf(m, "max GPU freq: %d MHz\n",
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intel_gpu_freq(rps, rps->max_freq));
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seq_printf(m, "min GPU freq: %d MHz\n",
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intel_gpu_freq(rps, rps->min_freq));
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seq_printf(m, "idle GPU freq: %d MHz\n",
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intel_gpu_freq(rps, rps->idle_freq));
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seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
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intel_gpu_freq(rps, rps->efficient_freq));
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} else if (GRAPHICS_VER(i915) >= 6) {
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u32 rp_state_limits;
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u32 gt_perf_status;
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u32 rp_state_cap;
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u32 rpmodectl, rpinclimit, rpdeclimit;
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u32 rpstat, cagf, reqf;
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u32 rpcurupei, rpcurup, rpprevup;
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u32 rpcurdownei, rpcurdown, rpprevdown;
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u32 rpupei, rpupt, rpdownei, rpdownt;
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u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
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int max_freq;
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rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
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if (IS_GEN9_LP(i915)) {
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rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
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gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
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} else {
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rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
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gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
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}
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/* RPSTAT1 is in the GT power well */
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intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
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reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
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if (GRAPHICS_VER(i915) >= 9) {
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reqf >>= 23;
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} else {
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reqf &= ~GEN6_TURBO_DISABLE;
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if (IS_HASWELL(i915) || IS_BROADWELL(i915))
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reqf >>= 24;
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else
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reqf >>= 25;
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}
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reqf = intel_gpu_freq(rps, reqf);
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rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
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rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
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rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
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rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
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rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
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rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
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rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
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rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
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rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
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rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
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rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
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rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
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rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
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rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
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cagf = intel_rps_read_actual_frequency(rps);
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intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
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if (GRAPHICS_VER(i915) >= 11) {
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pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
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pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
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/*
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* The equivalent to the PM ISR & IIR cannot be read
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* without affecting the current state of the system
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*/
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pm_isr = 0;
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pm_iir = 0;
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} else if (GRAPHICS_VER(i915) >= 8) {
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pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
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pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
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pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
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pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
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} else {
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pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
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pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
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pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
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pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
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}
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pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
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seq_printf(m, "Video Turbo Mode: %s\n",
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yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
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seq_printf(m, "HW control enabled: %s\n",
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yesno(rpmodectl & GEN6_RP_ENABLE));
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seq_printf(m, "SW control enabled: %s\n",
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yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
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GEN6_RP_MEDIA_SW_MODE));
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seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
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pm_ier, pm_imr, pm_mask);
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if (GRAPHICS_VER(i915) <= 10)
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seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
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pm_isr, pm_iir);
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seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
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rps->pm_intrmsk_mbz);
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seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
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seq_printf(m, "Render p-state ratio: %d\n",
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(gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
|
|
seq_printf(m, "Render p-state VID: %d\n",
|
|
gt_perf_status & 0xff);
|
|
seq_printf(m, "Render p-state limit: %d\n",
|
|
rp_state_limits & 0xff);
|
|
seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
|
|
seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
|
|
seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
|
|
seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
|
|
seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
|
|
seq_printf(m, "CAGF: %dMHz\n", cagf);
|
|
seq_printf(m, "RP CUR UP EI: %d (%lldns)\n",
|
|
rpcurupei,
|
|
intel_gt_pm_interval_to_ns(gt, rpcurupei));
|
|
seq_printf(m, "RP CUR UP: %d (%lldns)\n",
|
|
rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
|
|
seq_printf(m, "RP PREV UP: %d (%lldns)\n",
|
|
rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
|
|
seq_printf(m, "Up threshold: %d%%\n",
|
|
rps->power.up_threshold);
|
|
seq_printf(m, "RP UP EI: %d (%lldns)\n",
|
|
rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
|
|
seq_printf(m, "RP UP THRESHOLD: %d (%lldns)\n",
|
|
rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
|
|
|
|
seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n",
|
|
rpcurdownei,
|
|
intel_gt_pm_interval_to_ns(gt, rpcurdownei));
|
|
seq_printf(m, "RP CUR DOWN: %d (%lldns)\n",
|
|
rpcurdown,
|
|
intel_gt_pm_interval_to_ns(gt, rpcurdown));
|
|
seq_printf(m, "RP PREV DOWN: %d (%lldns)\n",
|
|
rpprevdown,
|
|
intel_gt_pm_interval_to_ns(gt, rpprevdown));
|
|
seq_printf(m, "Down threshold: %d%%\n",
|
|
rps->power.down_threshold);
|
|
seq_printf(m, "RP DOWN EI: %d (%lldns)\n",
|
|
rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
|
|
seq_printf(m, "RP DOWN THRESHOLD: %d (%lldns)\n",
|
|
rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
|
|
|
|
max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
|
|
rp_state_cap >> 16) & 0xff;
|
|
max_freq *= (IS_GEN9_BC(i915) ||
|
|
GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
|
|
seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
|
|
intel_gpu_freq(rps, max_freq));
|
|
|
|
max_freq = (rp_state_cap & 0xff00) >> 8;
|
|
max_freq *= (IS_GEN9_BC(i915) ||
|
|
GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
|
|
seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
|
|
intel_gpu_freq(rps, max_freq));
|
|
|
|
max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
|
|
rp_state_cap >> 0) & 0xff;
|
|
max_freq *= (IS_GEN9_BC(i915) ||
|
|
GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
|
|
seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
|
|
intel_gpu_freq(rps, max_freq));
|
|
seq_printf(m, "Max overclocked frequency: %dMHz\n",
|
|
intel_gpu_freq(rps, rps->max_freq));
|
|
|
|
seq_printf(m, "Current freq: %d MHz\n",
|
|
intel_gpu_freq(rps, rps->cur_freq));
|
|
seq_printf(m, "Actual freq: %d MHz\n", cagf);
|
|
seq_printf(m, "Idle freq: %d MHz\n",
|
|
intel_gpu_freq(rps, rps->idle_freq));
|
|
seq_printf(m, "Min freq: %d MHz\n",
|
|
intel_gpu_freq(rps, rps->min_freq));
|
|
seq_printf(m, "Boost freq: %d MHz\n",
|
|
intel_gpu_freq(rps, rps->boost_freq));
|
|
seq_printf(m, "Max freq: %d MHz\n",
|
|
intel_gpu_freq(rps, rps->max_freq));
|
|
seq_printf(m,
|
|
"efficient (RPe) frequency: %d MHz\n",
|
|
intel_gpu_freq(rps, rps->efficient_freq));
|
|
} else {
|
|
seq_puts(m, "no P-state info available\n");
|
|
}
|
|
|
|
seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk);
|
|
seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq);
|
|
seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
|
|
|
|
intel_runtime_pm_put(uncore->rpm, wakeref);
|
|
|
|
return 0;
|
|
}
|
|
DEFINE_GT_DEBUGFS_ATTRIBUTE(frequency);
|
|
|
|
static int llc_show(struct seq_file *m, void *data)
|
|
{
|
|
struct intel_gt *gt = m->private;
|
|
struct drm_i915_private *i915 = gt->i915;
|
|
const bool edram = GRAPHICS_VER(i915) > 8;
|
|
struct intel_rps *rps = >->rps;
|
|
unsigned int max_gpu_freq, min_gpu_freq;
|
|
intel_wakeref_t wakeref;
|
|
int gpu_freq, ia_freq;
|
|
|
|
seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(i915)));
|
|
seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC",
|
|
i915->edram_size_mb);
|
|
|
|
min_gpu_freq = rps->min_freq;
|
|
max_gpu_freq = rps->max_freq;
|
|
if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
|
|
/* Convert GT frequency to 50 HZ units */
|
|
min_gpu_freq /= GEN9_FREQ_SCALER;
|
|
max_gpu_freq /= GEN9_FREQ_SCALER;
|
|
}
|
|
|
|
seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
|
|
|
|
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
|
|
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
|
|
ia_freq = gpu_freq;
|
|
sandybridge_pcode_read(i915,
|
|
GEN6_PCODE_READ_MIN_FREQ_TABLE,
|
|
&ia_freq, NULL);
|
|
seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
|
|
intel_gpu_freq(rps,
|
|
(gpu_freq *
|
|
(IS_GEN9_BC(i915) ||
|
|
GRAPHICS_VER(i915) >= 10 ?
|
|
GEN9_FREQ_SCALER : 1))),
|
|
((ia_freq >> 0) & 0xff) * 100,
|
|
((ia_freq >> 8) & 0xff) * 100);
|
|
}
|
|
intel_runtime_pm_put(gt->uncore->rpm, wakeref);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool llc_eval(void *data)
|
|
{
|
|
struct intel_gt *gt = data;
|
|
|
|
return HAS_LLC(gt->i915);
|
|
}
|
|
|
|
DEFINE_GT_DEBUGFS_ATTRIBUTE(llc);
|
|
|
|
static const char *rps_power_to_str(unsigned int power)
|
|
{
|
|
static const char * const strings[] = {
|
|
[LOW_POWER] = "low power",
|
|
[BETWEEN] = "mixed",
|
|
[HIGH_POWER] = "high power",
|
|
};
|
|
|
|
if (power >= ARRAY_SIZE(strings) || !strings[power])
|
|
return "unknown";
|
|
|
|
return strings[power];
|
|
}
|
|
|
|
static int rps_boost_show(struct seq_file *m, void *data)
|
|
{
|
|
struct intel_gt *gt = m->private;
|
|
struct drm_i915_private *i915 = gt->i915;
|
|
struct intel_rps *rps = >->rps;
|
|
|
|
seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
|
|
seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
|
|
seq_printf(m, "GPU busy? %s, %llums\n",
|
|
yesno(gt->awake),
|
|
ktime_to_ms(intel_gt_get_awake_time(gt)));
|
|
seq_printf(m, "Boosts outstanding? %d\n",
|
|
atomic_read(&rps->num_waiters));
|
|
seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
|
|
seq_printf(m, "Frequency requested %d, actual %d\n",
|
|
intel_gpu_freq(rps, rps->cur_freq),
|
|
intel_rps_read_actual_frequency(rps));
|
|
seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
|
|
intel_gpu_freq(rps, rps->min_freq),
|
|
intel_gpu_freq(rps, rps->min_freq_softlimit),
|
|
intel_gpu_freq(rps, rps->max_freq_softlimit),
|
|
intel_gpu_freq(rps, rps->max_freq));
|
|
seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
|
|
intel_gpu_freq(rps, rps->idle_freq),
|
|
intel_gpu_freq(rps, rps->efficient_freq),
|
|
intel_gpu_freq(rps, rps->boost_freq));
|
|
|
|
seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
|
|
|
|
if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) {
|
|
struct intel_uncore *uncore = gt->uncore;
|
|
u32 rpup, rpupei;
|
|
u32 rpdown, rpdownei;
|
|
|
|
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
|
|
rpup = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
|
|
rpupei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
|
|
rpdown = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
|
|
rpdownei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
|
|
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
|
|
|
|
seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
|
|
rps_power_to_str(rps->power.mode));
|
|
seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
|
|
rpup && rpupei ? 100 * rpup / rpupei : 0,
|
|
rps->power.up_threshold);
|
|
seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
|
|
rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
|
|
rps->power.down_threshold);
|
|
} else {
|
|
seq_puts(m, "\nRPS Autotuning inactive\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool rps_eval(void *data)
|
|
{
|
|
struct intel_gt *gt = data;
|
|
|
|
return HAS_RPS(gt->i915);
|
|
}
|
|
|
|
DEFINE_GT_DEBUGFS_ATTRIBUTE(rps_boost);
|
|
|
|
void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root)
|
|
{
|
|
static const struct debugfs_gt_file files[] = {
|
|
{ "drpc", &drpc_fops, NULL },
|
|
{ "frequency", &frequency_fops, NULL },
|
|
{ "forcewake", &fw_domains_fops, NULL },
|
|
{ "llc", &llc_fops, llc_eval },
|
|
{ "rps_boost", &rps_boost_fops, rps_eval },
|
|
};
|
|
|
|
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
|
|
}
|