256 lines
7.0 KiB
C
256 lines
7.0 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Christian König.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König
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*/
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_reg.h"
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#include "radeon_asic.h"
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#include "atom.h"
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/*
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* check if enc_priv stores radeon_encoder_atom_dig
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*/
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static bool radeon_dig_encoder(struct drm_encoder *encoder)
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{
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_LVDS:
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case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
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case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
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case ENCODER_OBJECT_ID_INTERNAL_DVO1:
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
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case ENCODER_OBJECT_ID_INTERNAL_DDI:
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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return true;
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}
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return false;
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}
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/*
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* check if the chipset is supported
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*/
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static int r600_audio_chipset_supported(struct radeon_device *rdev)
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{
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return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE6(rdev))
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|| rdev->family == CHIP_RS600
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|| rdev->family == CHIP_RS690
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|| rdev->family == CHIP_RS740;
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}
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struct r600_audio r600_audio_status(struct radeon_device *rdev)
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{
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struct r600_audio status;
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uint32_t value;
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value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
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/* number of channels */
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status.channels = (value & 0x7) + 1;
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/* bits per sample */
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switch ((value & 0xF0) >> 4) {
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case 0x0:
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status.bits_per_sample = 8;
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break;
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case 0x1:
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status.bits_per_sample = 16;
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break;
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case 0x2:
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status.bits_per_sample = 20;
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break;
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case 0x3:
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status.bits_per_sample = 24;
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break;
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case 0x4:
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status.bits_per_sample = 32;
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break;
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default:
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dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
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(int)value);
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status.bits_per_sample = 16;
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}
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/* current sampling rate in HZ */
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if (value & 0x4000)
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status.rate = 44100;
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else
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status.rate = 48000;
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status.rate *= ((value >> 11) & 0x7) + 1;
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status.rate /= ((value >> 8) & 0x7) + 1;
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value = RREG32(R600_AUDIO_STATUS_BITS);
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/* iec 60958 status bits */
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status.status_bits = value & 0xff;
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/* iec 60958 category code */
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status.category_code = (value >> 8) & 0xff;
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return status;
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}
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/*
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* update all hdmi interfaces with current audio parameters
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*/
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void r600_audio_update_hdmi(struct work_struct *work)
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{
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struct radeon_device *rdev = container_of(work, struct radeon_device,
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audio_work);
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struct drm_device *dev = rdev->ddev;
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struct r600_audio audio_status = r600_audio_status(rdev);
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struct drm_encoder *encoder;
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bool changed = false;
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if (rdev->audio_status.channels != audio_status.channels ||
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rdev->audio_status.rate != audio_status.rate ||
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rdev->audio_status.bits_per_sample != audio_status.bits_per_sample ||
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rdev->audio_status.status_bits != audio_status.status_bits ||
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rdev->audio_status.category_code != audio_status.category_code) {
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rdev->audio_status = audio_status;
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changed = true;
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}
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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if (!radeon_dig_encoder(encoder))
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continue;
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if (changed || r600_hdmi_buffer_status_changed(encoder))
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r600_hdmi_update_audio_settings(encoder);
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}
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}
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/*
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* turn on/off audio engine
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*/
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static void r600_audio_engine_enable(struct radeon_device *rdev, bool enable)
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{
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u32 value = 0;
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DRM_INFO("%s audio support\n", enable ? "Enabling" : "Disabling");
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if (ASIC_IS_DCE4(rdev)) {
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if (enable) {
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value |= 0x81000000; /* Required to enable audio */
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value |= 0x0e1000f0; /* fglrx sets that too */
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}
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WREG32(EVERGREEN_AUDIO_ENABLE, value);
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} else {
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WREG32_P(R600_AUDIO_ENABLE,
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enable ? 0x81000000 : 0x0, ~0x81000000);
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}
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rdev->audio_enabled = enable;
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}
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/*
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* initialize the audio vars
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*/
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int r600_audio_init(struct radeon_device *rdev)
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{
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if (!radeon_audio || !r600_audio_chipset_supported(rdev))
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return 0;
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r600_audio_engine_enable(rdev, true);
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rdev->audio_status.channels = -1;
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rdev->audio_status.rate = -1;
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rdev->audio_status.bits_per_sample = -1;
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rdev->audio_status.status_bits = 0;
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rdev->audio_status.category_code = 0;
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return 0;
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}
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/*
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* atach the audio codec to the clock source of the encoder
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*/
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void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
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int base_rate = 48000;
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
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case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
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WREG32_P(R600_AUDIO_TIMING, 0, ~0x301);
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
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WREG32_P(R600_AUDIO_TIMING, 0x100, ~0x301);
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break;
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default:
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dev_err(rdev->dev, "Unsupported encoder type 0x%02X\n",
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radeon_encoder->encoder_id);
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return;
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}
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if (ASIC_IS_DCE4(rdev)) {
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/* TODO: other PLLs? */
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WREG32(EVERGREEN_AUDIO_PLL1_MUL, base_rate * 10);
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WREG32(EVERGREEN_AUDIO_PLL1_DIV, clock * 10);
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WREG32(EVERGREEN_AUDIO_PLL1_UNK, 0x00000071);
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/* Select DTO source */
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WREG32(0x5ac, radeon_crtc->crtc_id);
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} else {
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switch (dig->dig_encoder) {
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case 0:
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WREG32(R600_AUDIO_PLL1_MUL, base_rate * 50);
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WREG32(R600_AUDIO_PLL1_DIV, clock * 100);
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WREG32(R600_AUDIO_CLK_SRCSEL, 0);
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break;
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case 1:
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WREG32(R600_AUDIO_PLL2_MUL, base_rate * 50);
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WREG32(R600_AUDIO_PLL2_DIV, clock * 100);
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WREG32(R600_AUDIO_CLK_SRCSEL, 1);
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break;
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default:
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dev_err(rdev->dev,
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"Unsupported DIG on encoder 0x%02X\n",
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radeon_encoder->encoder_id);
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return;
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}
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}
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}
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/*
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* release the audio timer
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* TODO: How to do this correctly on SMP systems?
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*/
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void r600_audio_fini(struct radeon_device *rdev)
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{
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if (!rdev->audio_enabled)
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return;
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r600_audio_engine_enable(rdev, false);
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}
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