482 lines
14 KiB
C
482 lines
14 KiB
C
/*
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* Copyright (c) 2008-2010 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/**
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* DOC: Programming Atheros 802.11n analog front end radios
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*
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* AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
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* devices have either an external AR2133 analog front end radio for single
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* band 2.4 GHz communication or an AR5133 analog front end radio for dual
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* band 2.4 GHz / 5 GHz communication.
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*
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* All devices after the AR5416 and AR5418 family starting with the AR9280
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* have their analog front radios, MAC/BB and host PCIe/USB interface embedded
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* into a single-chip and require less programming.
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*
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* The following single-chips exist with a respective embedded radio:
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*
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* AR9280 - 11n dual-band 2x2 MIMO for PCIe
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* AR9281 - 11n single-band 1x2 MIMO for PCIe
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* AR9285 - 11n single-band 1x1 for PCIe
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* AR9287 - 11n single-band 2x2 MIMO for PCIe
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*
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* AR9220 - 11n dual-band 2x2 MIMO for PCI
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* AR9223 - 11n single-band 2x2 MIMO for PCI
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*
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* AR9287 - 11n single-band 1x1 MIMO for USB
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*/
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#include "hw.h"
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#include "ar9002_phy.h"
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/**
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* ar9002_hw_set_channel - set channel on single-chip device
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* @ah: atheros hardware structure
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* @chan:
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*
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* This is the function to change channel on single-chip devices, that is
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* all devices after ar9280.
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*
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* This function takes the channel value in MHz and sets
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* hardware channel value. Assumes writes have been enabled to analog bus.
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*
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* Actual Expression,
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*
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* For 2GHz channel,
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* Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
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* (freq_ref = 40MHz)
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*
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* For 5GHz channel,
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* Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
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* (freq_ref = 40MHz/(24>>amodeRefSel))
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*/
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static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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u16 bMode, fracMode, aModeRefSel = 0;
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u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
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struct chan_centers centers;
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u32 refDivA = 24;
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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freq = centers.synth_center;
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reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
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reg32 &= 0xc0000000;
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if (freq < 4800) { /* 2 GHz, fractional mode */
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u32 txctl;
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int regWrites = 0;
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bMode = 1;
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fracMode = 1;
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aModeRefSel = 0;
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channelSel = (freq * 0x10000) / 15;
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if (AR_SREV_9287_11_OR_LATER(ah)) {
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if (freq == 2484) {
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/* Enable channel spreading for channel 14 */
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REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
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1, regWrites);
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} else {
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REG_WRITE_ARRAY(&ah->iniCckfirNormal,
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1, regWrites);
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}
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} else {
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txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
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if (freq == 2484) {
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/* Enable channel spreading for channel 14 */
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REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
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txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
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} else {
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REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
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txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
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}
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}
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} else {
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bMode = 0;
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fracMode = 0;
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switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
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case 0:
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if ((freq % 20) == 0)
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aModeRefSel = 3;
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else if ((freq % 10) == 0)
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aModeRefSel = 2;
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if (aModeRefSel)
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break;
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case 1:
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default:
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aModeRefSel = 0;
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/*
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* Enable 2G (fractional) mode for channels
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* which are 5MHz spaced.
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*/
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fracMode = 1;
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refDivA = 1;
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channelSel = (freq * 0x8000) / 15;
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/* RefDivA setting */
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REG_RMW_FIELD(ah, AR_AN_SYNTH9,
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AR_AN_SYNTH9_REFDIVA, refDivA);
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}
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if (!fracMode) {
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ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
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channelSel = ndiv & 0x1ff;
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channelFrac = (ndiv & 0xfffffe00) * 2;
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channelSel = (channelSel << 17) | channelFrac;
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}
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}
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reg32 = reg32 |
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(bMode << 29) |
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(fracMode << 28) | (aModeRefSel << 26) | (channelSel);
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REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
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ah->curchan = chan;
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ah->curchan_rad_index = -1;
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return 0;
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}
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/**
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* ar9002_hw_spur_mitigate - convert baseband spur frequency
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* @ah: atheros hardware structure
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* @chan:
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*
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* For single-chip solutions. Converts to baseband spur frequency given the
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* input channel frequency and compute register settings below.
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*/
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static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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int bb_spur = AR_NO_SPUR;
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int freq;
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int bin, cur_bin;
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int bb_spur_off, spur_subchannel_sd;
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int spur_freq_sd;
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int spur_delta_phase;
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int denominator;
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int upper, lower, cur_vit_mask;
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int tmp, newVal;
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int i;
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int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
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AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
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};
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int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
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AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
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};
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int inc[4] = { 0, 100, 0, 0 };
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struct chan_centers centers;
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int8_t mask_m[123];
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int8_t mask_p[123];
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int8_t mask_amt;
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int tmp_mask;
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int cur_bb_spur;
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bool is2GHz = IS_CHAN_2GHZ(chan);
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memset(&mask_m, 0, sizeof(int8_t) * 123);
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memset(&mask_p, 0, sizeof(int8_t) * 123);
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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freq = centers.synth_center;
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ah->config.spurmode = SPUR_ENABLE_EEPROM;
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for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
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if (is2GHz)
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cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
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else
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cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
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if (AR_NO_SPUR == cur_bb_spur)
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break;
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cur_bb_spur = cur_bb_spur - freq;
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if (IS_CHAN_HT40(chan)) {
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if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
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(cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
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bb_spur = cur_bb_spur;
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break;
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}
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} else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
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(cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
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bb_spur = cur_bb_spur;
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break;
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}
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}
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if (AR_NO_SPUR == bb_spur) {
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REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
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AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
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return;
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} else {
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REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
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AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
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}
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bin = bb_spur * 320;
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tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
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newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
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AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
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AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
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AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
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REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
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newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
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AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
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AR_PHY_SPUR_REG_MASK_RATE_SELECT |
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AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
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SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
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REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
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if (IS_CHAN_HT40(chan)) {
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if (bb_spur < 0) {
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spur_subchannel_sd = 1;
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bb_spur_off = bb_spur + 10;
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} else {
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spur_subchannel_sd = 0;
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bb_spur_off = bb_spur - 10;
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}
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} else {
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spur_subchannel_sd = 0;
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bb_spur_off = bb_spur;
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}
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if (IS_CHAN_HT40(chan))
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spur_delta_phase =
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((bb_spur * 262144) /
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10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
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else
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spur_delta_phase =
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((bb_spur * 524288) /
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10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
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denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
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spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
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newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
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SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
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SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
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REG_WRITE(ah, AR_PHY_TIMING11, newVal);
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newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
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REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
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cur_bin = -6000;
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upper = bin + 100;
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lower = bin - 100;
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for (i = 0; i < 4; i++) {
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int pilot_mask = 0;
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int chan_mask = 0;
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int bp = 0;
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for (bp = 0; bp < 30; bp++) {
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if ((cur_bin > lower) && (cur_bin < upper)) {
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pilot_mask = pilot_mask | 0x1 << bp;
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chan_mask = chan_mask | 0x1 << bp;
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}
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cur_bin += 100;
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}
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cur_bin += inc[i];
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REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
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REG_WRITE(ah, chan_mask_reg[i], chan_mask);
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}
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cur_vit_mask = 6100;
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upper = bin + 120;
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lower = bin - 120;
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for (i = 0; i < 123; i++) {
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if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
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/* workaround for gcc bug #37014 */
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volatile int tmp_v = abs(cur_vit_mask - bin);
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if (tmp_v < 75)
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mask_amt = 1;
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else
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mask_amt = 0;
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if (cur_vit_mask < 0)
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mask_m[abs(cur_vit_mask / 100)] = mask_amt;
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else
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mask_p[cur_vit_mask / 100] = mask_amt;
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}
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cur_vit_mask -= 100;
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}
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tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
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| (mask_m[48] << 26) | (mask_m[49] << 24)
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| (mask_m[50] << 22) | (mask_m[51] << 20)
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| (mask_m[52] << 18) | (mask_m[53] << 16)
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| (mask_m[54] << 14) | (mask_m[55] << 12)
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| (mask_m[56] << 10) | (mask_m[57] << 8)
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| (mask_m[58] << 6) | (mask_m[59] << 4)
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| (mask_m[60] << 2) | (mask_m[61] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
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REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
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tmp_mask = (mask_m[31] << 28)
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| (mask_m[32] << 26) | (mask_m[33] << 24)
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| (mask_m[34] << 22) | (mask_m[35] << 20)
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| (mask_m[36] << 18) | (mask_m[37] << 16)
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| (mask_m[48] << 14) | (mask_m[39] << 12)
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| (mask_m[40] << 10) | (mask_m[41] << 8)
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| (mask_m[42] << 6) | (mask_m[43] << 4)
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| (mask_m[44] << 2) | (mask_m[45] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
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tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
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| (mask_m[18] << 26) | (mask_m[18] << 24)
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| (mask_m[20] << 22) | (mask_m[20] << 20)
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| (mask_m[22] << 18) | (mask_m[22] << 16)
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| (mask_m[24] << 14) | (mask_m[24] << 12)
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| (mask_m[25] << 10) | (mask_m[26] << 8)
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| (mask_m[27] << 6) | (mask_m[28] << 4)
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| (mask_m[29] << 2) | (mask_m[30] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
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tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
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| (mask_m[2] << 26) | (mask_m[3] << 24)
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| (mask_m[4] << 22) | (mask_m[5] << 20)
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| (mask_m[6] << 18) | (mask_m[7] << 16)
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| (mask_m[8] << 14) | (mask_m[9] << 12)
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| (mask_m[10] << 10) | (mask_m[11] << 8)
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| (mask_m[12] << 6) | (mask_m[13] << 4)
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| (mask_m[14] << 2) | (mask_m[15] << 0);
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REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
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tmp_mask = (mask_p[15] << 28)
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| (mask_p[14] << 26) | (mask_p[13] << 24)
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| (mask_p[12] << 22) | (mask_p[11] << 20)
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| (mask_p[10] << 18) | (mask_p[9] << 16)
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| (mask_p[8] << 14) | (mask_p[7] << 12)
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| (mask_p[6] << 10) | (mask_p[5] << 8)
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| (mask_p[4] << 6) | (mask_p[3] << 4)
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| (mask_p[2] << 2) | (mask_p[1] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
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tmp_mask = (mask_p[30] << 28)
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| (mask_p[29] << 26) | (mask_p[28] << 24)
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| (mask_p[27] << 22) | (mask_p[26] << 20)
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| (mask_p[25] << 18) | (mask_p[24] << 16)
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| (mask_p[23] << 14) | (mask_p[22] << 12)
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| (mask_p[21] << 10) | (mask_p[20] << 8)
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| (mask_p[19] << 6) | (mask_p[18] << 4)
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| (mask_p[17] << 2) | (mask_p[16] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
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tmp_mask = (mask_p[45] << 28)
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| (mask_p[44] << 26) | (mask_p[43] << 24)
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| (mask_p[42] << 22) | (mask_p[41] << 20)
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| (mask_p[40] << 18) | (mask_p[39] << 16)
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| (mask_p[38] << 14) | (mask_p[37] << 12)
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| (mask_p[36] << 10) | (mask_p[35] << 8)
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| (mask_p[34] << 6) | (mask_p[33] << 4)
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| (mask_p[32] << 2) | (mask_p[31] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
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tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
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| (mask_p[59] << 26) | (mask_p[58] << 24)
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| (mask_p[57] << 22) | (mask_p[56] << 20)
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| (mask_p[55] << 18) | (mask_p[54] << 16)
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| (mask_p[53] << 14) | (mask_p[52] << 12)
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| (mask_p[51] << 10) | (mask_p[50] << 8)
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| (mask_p[49] << 6) | (mask_p[48] << 4)
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| (mask_p[47] << 2) | (mask_p[46] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
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}
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static void ar9002_olc_init(struct ath_hw *ah)
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{
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u32 i;
|
|
|
|
if (!OLC_FOR_AR9280_20_LATER)
|
|
return;
|
|
|
|
if (OLC_FOR_AR9287_10_LATER) {
|
|
REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
|
|
AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
|
|
ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
|
|
AR9287_AN_TXPC0_TXPCMODE,
|
|
AR9287_AN_TXPC0_TXPCMODE_S,
|
|
AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
|
|
udelay(100);
|
|
} else {
|
|
for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
|
|
ah->originalGain[i] =
|
|
MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
|
|
AR_PHY_TX_GAIN);
|
|
ah->PDADCdelta = 0;
|
|
}
|
|
}
|
|
|
|
static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
|
|
struct ath9k_channel *chan)
|
|
{
|
|
u32 pll;
|
|
|
|
pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
|
|
|
|
if (chan && IS_CHAN_HALF_RATE(chan))
|
|
pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
|
|
else if (chan && IS_CHAN_QUARTER_RATE(chan))
|
|
pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
|
|
|
|
if (chan && IS_CHAN_5GHZ(chan)) {
|
|
pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
|
|
|
|
|
|
if (AR_SREV_9280_20(ah)) {
|
|
if (((chan->channel % 20) == 0)
|
|
|| ((chan->channel % 10) == 0))
|
|
pll = 0x2850;
|
|
else
|
|
pll = 0x142c;
|
|
}
|
|
} else {
|
|
pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
|
|
}
|
|
|
|
return pll;
|
|
}
|
|
|
|
void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
|
|
{
|
|
struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
|
|
|
|
priv_ops->set_rf_regs = NULL;
|
|
priv_ops->rf_alloc_ext_banks = NULL;
|
|
priv_ops->rf_free_ext_banks = NULL;
|
|
priv_ops->rf_set_freq = ar9002_hw_set_channel;
|
|
priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
|
|
priv_ops->olc_init = ar9002_olc_init;
|
|
priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
|
|
}
|