289 lines
7.1 KiB
ArmAsm
289 lines
7.1 KiB
ArmAsm
/*
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* ppc64 MMU hashtable management routines
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*
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* (c) Copyright IBM Corp. 2003
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*
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* Maintained by: Benjamin Herrenschmidt
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* <benh@kernel.crashing.org>
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*
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* This file is covered by the GNU Public Licence v2 as
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* described in the kernel's COPYING file.
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*/
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/page.h>
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#include <asm/types.h>
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#include <asm/ppc_asm.h>
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#include <asm/offsets.h>
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#include <asm/cputable.h>
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.text
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/*
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* Stackframe:
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*
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* +-> Back chain (SP + 256)
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* | General register save area (SP + 112)
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* | Parameter save area (SP + 48)
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* | TOC save area (SP + 40)
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* | link editor doubleword (SP + 32)
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* | compiler doubleword (SP + 24)
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* | LR save area (SP + 16)
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* | CR save area (SP + 8)
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* SP ---> +-- Back chain (SP + 0)
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*/
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#define STACKFRAMESIZE 256
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/* Save parameters offsets */
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#define STK_PARM(i) (STACKFRAMESIZE + 48 + ((i)-3)*8)
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/* Save non-volatile offsets */
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#define STK_REG(i) (112 + ((i)-14)*8)
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/*
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* _hash_page(unsigned long ea, unsigned long access, unsigned long vsid,
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* pte_t *ptep, unsigned long trap, int local)
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*
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* Adds a page to the hash table. This is the non-LPAR version for now
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*/
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_GLOBAL(__hash_page)
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mflr r0
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std r0,16(r1)
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stdu r1,-STACKFRAMESIZE(r1)
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/* Save all params that we need after a function call */
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std r6,STK_PARM(r6)(r1)
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std r8,STK_PARM(r8)(r1)
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/* Add _PAGE_PRESENT to access */
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ori r4,r4,_PAGE_PRESENT
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/* Save non-volatile registers.
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* r31 will hold "old PTE"
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* r30 is "new PTE"
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* r29 is "va"
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* r28 is a hash value
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* r27 is hashtab mask (maybe dynamic patched instead ?)
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*/
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std r27,STK_REG(r27)(r1)
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std r28,STK_REG(r28)(r1)
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std r29,STK_REG(r29)(r1)
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std r30,STK_REG(r30)(r1)
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std r31,STK_REG(r31)(r1)
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/* Step 1:
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*
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* Check permissions, atomically mark the linux PTE busy
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* and hashed.
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*/
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1:
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ldarx r31,0,r6
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/* Check access rights (access & ~(pte_val(*ptep))) */
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andc. r0,r4,r31
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bne- htab_wrong_access
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/* Check if PTE is busy */
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andi. r0,r31,_PAGE_BUSY
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/* If so, just bail out and refault if needed. Someone else
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* is changing this PTE anyway and might hash it.
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*/
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bne- bail_ok
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/* Prepare new PTE value (turn access RW into DIRTY, then
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* add BUSY,HASHPTE and ACCESSED)
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*/
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rlwinm r30,r4,32-9+7,31-7,31-7 /* _PAGE_RW -> _PAGE_DIRTY */
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or r30,r30,r31
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ori r30,r30,_PAGE_BUSY | _PAGE_ACCESSED | _PAGE_HASHPTE
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/* Write the linux PTE atomically (setting busy) */
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stdcx. r30,0,r6
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bne- 1b
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isync
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/* Step 2:
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*
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* Insert/Update the HPTE in the hash table. At this point,
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* r4 (access) is re-useable, we use it for the new HPTE flags
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*/
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/* Calc va and put it in r29 */
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rldicr r29,r5,28,63-28
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rldicl r3,r3,0,36
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or r29,r3,r29
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/* Calculate hash value for primary slot and store it in r28 */
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rldicl r5,r5,0,25 /* vsid & 0x0000007fffffffff */
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rldicl r0,r3,64-12,48 /* (ea >> 12) & 0xffff */
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xor r28,r5,r0
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/* Convert linux PTE bits into HW equivalents */
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andi. r3,r30,0x1fe /* Get basic set of flags */
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xori r3,r3,HW_NO_EXEC /* _PAGE_EXEC -> NOEXEC */
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rlwinm r0,r30,32-9+1,30,30 /* _PAGE_RW -> _PAGE_USER (r0) */
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rlwinm r4,r30,32-7+1,30,30 /* _PAGE_DIRTY -> _PAGE_USER (r4) */
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and r0,r0,r4 /* _PAGE_RW & _PAGE_DIRTY -> r0 bit 30 */
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andc r0,r30,r0 /* r0 = pte & ~r0 */
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rlwimi r3,r0,32-1,31,31 /* Insert result into PP lsb */
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/* We eventually do the icache sync here (maybe inline that
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* code rather than call a C function...)
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*/
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BEGIN_FTR_SECTION
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mr r4,r30
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mr r5,r7
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bl .hash_page_do_lazy_icache
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END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
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/* At this point, r3 contains new PP bits, save them in
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* place of "access" in the param area (sic)
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*/
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std r3,STK_PARM(r4)(r1)
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/* Get htab_hash_mask */
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ld r4,htab_hash_mask@got(2)
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ld r27,0(r4) /* htab_hash_mask -> r27 */
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/* Check if we may already be in the hashtable, in this case, we
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* go to out-of-line code to try to modify the HPTE
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*/
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andi. r0,r31,_PAGE_HASHPTE
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bne htab_modify_pte
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htab_insert_pte:
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/* Clear hpte bits in new pte (we also clear BUSY btw) and
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* add _PAGE_HASHPTE
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*/
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lis r0,_PAGE_HPTEFLAGS@h
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ori r0,r0,_PAGE_HPTEFLAGS@l
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andc r30,r30,r0
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ori r30,r30,_PAGE_HASHPTE
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/* page number in r5 */
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rldicl r5,r31,64-PTE_SHIFT,PTE_SHIFT
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/* Calculate primary group hash */
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and r0,r28,r27
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rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */
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/* Call ppc_md.hpte_insert */
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ld r7,STK_PARM(r4)(r1) /* Retreive new pp bits */
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mr r4,r29 /* Retreive va */
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li r6,0 /* no vflags */
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_GLOBAL(htab_call_hpte_insert1)
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bl . /* Will be patched by htab_finish_init() */
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cmpdi 0,r3,0
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bge htab_pte_insert_ok /* Insertion successful */
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cmpdi 0,r3,-2 /* Critical failure */
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beq- htab_pte_insert_failure
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/* Now try secondary slot */
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/* page number in r5 */
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rldicl r5,r31,64-PTE_SHIFT,PTE_SHIFT
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/* Calculate secondary group hash */
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andc r0,r27,r28
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rldicr r3,r0,3,63-3 /* r0 = (~hash & mask) << 3 */
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/* Call ppc_md.hpte_insert */
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ld r7,STK_PARM(r4)(r1) /* Retreive new pp bits */
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mr r4,r29 /* Retreive va */
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li r6,HPTE_V_SECONDARY@l /* secondary slot */
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_GLOBAL(htab_call_hpte_insert2)
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bl . /* Will be patched by htab_finish_init() */
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cmpdi 0,r3,0
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bge+ htab_pte_insert_ok /* Insertion successful */
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cmpdi 0,r3,-2 /* Critical failure */
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beq- htab_pte_insert_failure
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/* Both are full, we need to evict something */
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mftb r0
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/* Pick a random group based on TB */
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andi. r0,r0,1
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mr r5,r28
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bne 2f
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not r5,r5
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2: and r0,r5,r27
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rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */
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/* Call ppc_md.hpte_remove */
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_GLOBAL(htab_call_hpte_remove)
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bl . /* Will be patched by htab_finish_init() */
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/* Try all again */
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b htab_insert_pte
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bail_ok:
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li r3,0
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b bail
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htab_pte_insert_ok:
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/* Insert slot number & secondary bit in PTE */
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rldimi r30,r3,12,63-15
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/* Write out the PTE with a normal write
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* (maybe add eieio may be good still ?)
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*/
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htab_write_out_pte:
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ld r6,STK_PARM(r6)(r1)
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std r30,0(r6)
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li r3, 0
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bail:
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ld r27,STK_REG(r27)(r1)
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ld r28,STK_REG(r28)(r1)
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ld r29,STK_REG(r29)(r1)
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ld r30,STK_REG(r30)(r1)
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ld r31,STK_REG(r31)(r1)
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addi r1,r1,STACKFRAMESIZE
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ld r0,16(r1)
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mtlr r0
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blr
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htab_modify_pte:
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/* Keep PP bits in r4 and slot idx from the PTE around in r3 */
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mr r4,r3
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rlwinm r3,r31,32-12,29,31
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/* Secondary group ? if yes, get a inverted hash value */
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mr r5,r28
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andi. r0,r31,_PAGE_SECONDARY
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beq 1f
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not r5,r5
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1:
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/* Calculate proper slot value for ppc_md.hpte_updatepp */
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and r0,r5,r27
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rldicr r0,r0,3,63-3 /* r0 = (hash & mask) << 3 */
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add r3,r0,r3 /* add slot idx */
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/* Call ppc_md.hpte_updatepp */
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mr r5,r29 /* va */
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li r6,0 /* large is 0 */
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ld r7,STK_PARM(r8)(r1) /* get "local" param */
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_GLOBAL(htab_call_hpte_updatepp)
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bl . /* Will be patched by htab_finish_init() */
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/* if we failed because typically the HPTE wasn't really here
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* we try an insertion.
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*/
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cmpdi 0,r3,-1
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beq- htab_insert_pte
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/* Clear the BUSY bit and Write out the PTE */
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li r0,_PAGE_BUSY
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andc r30,r30,r0
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b htab_write_out_pte
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htab_wrong_access:
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/* Bail out clearing reservation */
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stdcx. r31,0,r6
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li r3,1
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b bail
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htab_pte_insert_failure:
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/* Bail out restoring old PTE */
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ld r6,STK_PARM(r6)(r1)
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std r31,0(r6)
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li r3,-1
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b bail
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