1227 lines
36 KiB
C
1227 lines
36 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/circ_buf.h>
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#include "i915_drv.h"
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#include "intel_uc.h"
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#include <trace/events/dma_fence.h>
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/**
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* DOC: GuC-based command submission
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*
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* i915_guc_client:
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* We use the term client to avoid confusion with contexts. A i915_guc_client is
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* equivalent to GuC object guc_context_desc. This context descriptor is
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* allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
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* and workqueue for it. Also the process descriptor (guc_process_desc), which
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* is mapped to client space. So the client can write Work Item then ring the
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* doorbell.
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*
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* To simplify the implementation, we allocate one gem object that contains all
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* pages for doorbell, process descriptor and workqueue.
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*
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* The Scratch registers:
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* There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
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* a value to the action register (SOFT_SCRATCH_0) along with any data. It then
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* triggers an interrupt on the GuC via another register write (0xC4C8).
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* Firmware writes a success/fail code back to the action register after
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* processes the request. The kernel driver polls waiting for this update and
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* then proceeds.
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* See intel_guc_send()
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*
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* Doorbells:
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* Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
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* mapped into process space.
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*
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* Work Items:
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* There are several types of work items that the host may place into a
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* workqueue, each with its own requirements and limitations. Currently only
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* WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
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* represents in-order queue. The kernel driver packs ring tail pointer and an
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* ELSP context descriptor dword into Work Item.
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* See guc_wq_item_append()
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*
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*/
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/*
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* Tell the GuC to allocate or deallocate a specific doorbell
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*/
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static int guc_allocate_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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u32 action[] = {
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INTEL_GUC_ACTION_ALLOCATE_DOORBELL,
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client->ctx_index
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};
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return intel_guc_send(guc, action, ARRAY_SIZE(action));
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}
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static int guc_release_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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u32 action[] = {
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INTEL_GUC_ACTION_DEALLOCATE_DOORBELL,
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client->ctx_index
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};
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return intel_guc_send(guc, action, ARRAY_SIZE(action));
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}
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/*
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* Initialise, update, or clear doorbell data shared with the GuC
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*
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* These functions modify shared data and so need access to the mapped
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* client object which contains the page being used for the doorbell
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*/
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static int guc_update_doorbell_id(struct intel_guc *guc,
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struct i915_guc_client *client,
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u16 new_id)
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{
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struct sg_table *sg = guc->ctx_pool_vma->pages;
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void *doorbell_bitmap = guc->doorbell_bitmap;
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struct guc_doorbell_info *doorbell;
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struct guc_context_desc desc;
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size_t len;
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doorbell = client->vaddr + client->doorbell_offset;
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if (client->doorbell_id != GUC_INVALID_DOORBELL_ID &&
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test_bit(client->doorbell_id, doorbell_bitmap)) {
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/* Deactivate the old doorbell */
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doorbell->db_status = GUC_DOORBELL_DISABLED;
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(void)guc_release_doorbell(guc, client);
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__clear_bit(client->doorbell_id, doorbell_bitmap);
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}
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/* Update the GuC's idea of the doorbell ID */
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len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
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sizeof(desc) * client->ctx_index);
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if (len != sizeof(desc))
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return -EFAULT;
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desc.db_id = new_id;
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len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
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sizeof(desc) * client->ctx_index);
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if (len != sizeof(desc))
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return -EFAULT;
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client->doorbell_id = new_id;
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if (new_id == GUC_INVALID_DOORBELL_ID)
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return 0;
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/* Activate the new doorbell */
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__set_bit(new_id, doorbell_bitmap);
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doorbell->db_status = GUC_DOORBELL_ENABLED;
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doorbell->cookie = client->doorbell_cookie;
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return guc_allocate_doorbell(guc, client);
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}
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static void guc_disable_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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(void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID);
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/* XXX: wait for any interrupts */
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/* XXX: wait for workqueue to drain */
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}
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static uint16_t
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select_doorbell_register(struct intel_guc *guc, uint32_t priority)
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{
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/*
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* The bitmap tracks which doorbell registers are currently in use.
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* It is split into two halves; the first half is used for normal
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* priority contexts, the second half for high-priority ones.
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* Note that logically higher priorities are numerically less than
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* normal ones, so the test below means "is it high-priority?"
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*/
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const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
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const uint16_t half = GUC_MAX_DOORBELLS / 2;
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const uint16_t start = hi_pri ? half : 0;
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const uint16_t end = start + half;
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uint16_t id;
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id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
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if (id == end)
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id = GUC_INVALID_DOORBELL_ID;
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DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
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hi_pri ? "high" : "normal", id);
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return id;
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}
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/*
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* Select, assign and relase doorbell cachelines
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*
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* These functions track which doorbell cachelines are in use.
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* The data they manipulate is protected by the intel_guc_send lock.
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*/
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static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
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{
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const uint32_t cacheline_size = cache_line_size();
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uint32_t offset;
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/* Doorbell uses a single cache line within a page */
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offset = offset_in_page(guc->db_cacheline);
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/* Moving to next cache line to reduce contention */
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guc->db_cacheline += cacheline_size;
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DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
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offset, guc->db_cacheline, cacheline_size);
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return offset;
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}
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/*
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* Initialise the process descriptor shared with the GuC firmware.
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*/
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static void guc_proc_desc_init(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct guc_process_desc *desc;
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desc = client->vaddr + client->proc_desc_offset;
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memset(desc, 0, sizeof(*desc));
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/*
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* XXX: pDoorbell and WQVBaseAddress are pointers in process address
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* space for ring3 clients (set them as in mmap_ioctl) or kernel
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* space for kernel clients (map on demand instead? May make debug
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* easier to have it mapped).
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*/
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desc->wq_base_addr = 0;
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desc->db_base_addr = 0;
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desc->context_id = client->ctx_index;
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desc->wq_size_bytes = client->wq_size;
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desc->wq_status = WQ_STATUS_ACTIVE;
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desc->priority = client->priority;
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}
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/*
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* Initialise/clear the context descriptor shared with the GuC firmware.
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*
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* This descriptor tells the GuC where (in GGTT space) to find the important
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* data structures relating to this client (doorbell, process descriptor,
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* write queue, etc).
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*/
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static void guc_ctx_desc_init(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct intel_engine_cs *engine;
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struct i915_gem_context *ctx = client->owner;
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struct guc_context_desc desc;
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struct sg_table *sg;
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unsigned int tmp;
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u32 gfx_addr;
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memset(&desc, 0, sizeof(desc));
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desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
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desc.context_id = client->ctx_index;
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desc.priority = client->priority;
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desc.db_id = client->doorbell_id;
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for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
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struct intel_context *ce = &ctx->engine[engine->id];
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uint32_t guc_engine_id = engine->guc_id;
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struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id];
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/* TODO: We have a design issue to be solved here. Only when we
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* receive the first batch, we know which engine is used by the
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* user. But here GuC expects the lrc and ring to be pinned. It
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* is not an issue for default context, which is the only one
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* for now who owns a GuC client. But for future owner of GuC
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* client, need to make sure lrc is pinned prior to enter here.
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*/
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if (!ce->state)
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break; /* XXX: continue? */
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lrc->context_desc = lower_32_bits(ce->lrc_desc);
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/* The state page is after PPHWSP */
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lrc->ring_lcra =
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guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
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lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
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(guc_engine_id << GUC_ELC_ENGINE_OFFSET);
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lrc->ring_begin = guc_ggtt_offset(ce->ring->vma);
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lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
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lrc->ring_next_free_location = lrc->ring_begin;
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lrc->ring_current_tail_pointer_value = 0;
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desc.engines_used |= (1 << guc_engine_id);
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}
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DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
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client->engines, desc.engines_used);
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WARN_ON(desc.engines_used == 0);
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/*
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* The doorbell, process descriptor, and workqueue are all parts
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* of the client object, which the GuC will reference via the GGTT
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*/
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gfx_addr = guc_ggtt_offset(client->vma);
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desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
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client->doorbell_offset;
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desc.db_trigger_cpu =
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(uintptr_t)client->vaddr + client->doorbell_offset;
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desc.db_trigger_uk = gfx_addr + client->doorbell_offset;
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desc.process_desc = gfx_addr + client->proc_desc_offset;
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desc.wq_addr = gfx_addr + client->wq_offset;
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desc.wq_size = client->wq_size;
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/*
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* XXX: Take LRCs from an existing context if this is not an
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* IsKMDCreatedContext client
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*/
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desc.desc_private = (uintptr_t)client;
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/* Pool context is pinned already */
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sg = guc->ctx_pool_vma->pages;
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sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
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sizeof(desc) * client->ctx_index);
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}
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static void guc_ctx_desc_fini(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct guc_context_desc desc;
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struct sg_table *sg;
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memset(&desc, 0, sizeof(desc));
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sg = guc->ctx_pool_vma->pages;
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sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
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sizeof(desc) * client->ctx_index);
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}
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/**
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* i915_guc_wq_reserve() - reserve space in the GuC's workqueue
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* @request: request associated with the commands
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*
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* Return: 0 if space is available
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* -EAGAIN if space is not currently available
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*
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* This function must be called (and must return 0) before a request
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* is submitted to the GuC via i915_guc_submit() below. Once a result
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* of 0 has been returned, it must be balanced by a corresponding
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* call to submit().
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*
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* Reservation allows the caller to determine in advance that space
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* will be available for the next submission before committing resources
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* to it, and helps avoid late failures with complicated recovery paths.
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*/
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int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
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{
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const size_t wqi_size = sizeof(struct guc_wq_item);
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struct i915_guc_client *client = request->i915->guc.execbuf_client;
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struct guc_process_desc *desc = client->vaddr +
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client->proc_desc_offset;
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u32 freespace;
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int ret;
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spin_lock_irq(&client->wq_lock);
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freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
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freespace -= client->wq_rsvd;
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if (likely(freespace >= wqi_size)) {
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client->wq_rsvd += wqi_size;
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ret = 0;
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} else {
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client->no_wq_space++;
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ret = -EAGAIN;
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}
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spin_unlock_irq(&client->wq_lock);
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return ret;
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}
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static void guc_client_update_wq_rsvd(struct i915_guc_client *client, int size)
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{
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unsigned long flags;
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spin_lock_irqsave(&client->wq_lock, flags);
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client->wq_rsvd += size;
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spin_unlock_irqrestore(&client->wq_lock, flags);
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}
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void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
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{
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const int wqi_size = sizeof(struct guc_wq_item);
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struct i915_guc_client *client = request->i915->guc.execbuf_client;
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GEM_BUG_ON(READ_ONCE(client->wq_rsvd) < wqi_size);
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guc_client_update_wq_rsvd(client, -wqi_size);
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}
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/* Construct a Work Item and append it to the GuC's Work Queue */
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static void guc_wq_item_append(struct i915_guc_client *client,
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struct drm_i915_gem_request *rq)
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{
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/* wqi_len is in DWords, and does not include the one-word header */
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const size_t wqi_size = sizeof(struct guc_wq_item);
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const u32 wqi_len = wqi_size/sizeof(u32) - 1;
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struct intel_engine_cs *engine = rq->engine;
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struct guc_process_desc *desc;
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struct guc_wq_item *wqi;
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u32 freespace, tail, wq_off;
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desc = client->vaddr + client->proc_desc_offset;
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/* Free space is guaranteed, see i915_guc_wq_reserve() above */
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freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
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GEM_BUG_ON(freespace < wqi_size);
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/* The GuC firmware wants the tail index in QWords, not bytes */
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tail = rq->tail;
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GEM_BUG_ON(tail & 7);
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tail >>= 3;
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GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
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/* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
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* should not have the case where structure wqi is across page, neither
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* wrapped to the beginning. This simplifies the implementation below.
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*
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* XXX: if not the case, we need save data to a temp wqi and copy it to
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* workqueue buffer dw by dw.
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*/
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BUILD_BUG_ON(wqi_size != 16);
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GEM_BUG_ON(client->wq_rsvd < wqi_size);
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/* postincrement WQ tail for next time */
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wq_off = client->wq_tail;
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GEM_BUG_ON(wq_off & (wqi_size - 1));
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client->wq_tail += wqi_size;
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client->wq_tail &= client->wq_size - 1;
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client->wq_rsvd -= wqi_size;
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/* WQ starts from the page after doorbell / process_desc */
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wqi = client->vaddr + wq_off + GUC_DB_SIZE;
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/* Now fill in the 4-word work queue item */
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wqi->header = WQ_TYPE_INORDER |
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(wqi_len << WQ_LEN_SHIFT) |
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(engine->guc_id << WQ_TARGET_SHIFT) |
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WQ_NO_WCFLUSH_WAIT;
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/* The GuC wants only the low-order word of the context descriptor */
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wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine);
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wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
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wqi->fence_id = rq->global_seqno;
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}
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static int guc_ring_doorbell(struct i915_guc_client *client)
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{
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struct guc_process_desc *desc;
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union guc_doorbell_qw db_cmp, db_exc, db_ret;
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union guc_doorbell_qw *db;
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int attempt = 2, ret = -EAGAIN;
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desc = client->vaddr + client->proc_desc_offset;
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/* Update the tail so it is visible to GuC */
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desc->tail = client->wq_tail;
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/* current cookie */
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db_cmp.db_status = GUC_DOORBELL_ENABLED;
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db_cmp.cookie = client->doorbell_cookie;
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/* cookie to be updated */
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db_exc.db_status = GUC_DOORBELL_ENABLED;
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db_exc.cookie = client->doorbell_cookie + 1;
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if (db_exc.cookie == 0)
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db_exc.cookie = 1;
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|
|
/* pointer of current doorbell cacheline */
|
|
db = client->vaddr + client->doorbell_offset;
|
|
|
|
while (attempt--) {
|
|
/* lets ring the doorbell */
|
|
db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
|
|
db_cmp.value_qw, db_exc.value_qw);
|
|
|
|
/* if the exchange was successfully executed */
|
|
if (db_ret.value_qw == db_cmp.value_qw) {
|
|
/* db was successfully rung */
|
|
client->doorbell_cookie = db_exc.cookie;
|
|
ret = 0;
|
|
break;
|
|
}
|
|
|
|
/* XXX: doorbell was lost and need to acquire it again */
|
|
if (db_ret.db_status == GUC_DOORBELL_DISABLED)
|
|
break;
|
|
|
|
DRM_WARN("Cookie mismatch. Expected %d, found %d\n",
|
|
db_cmp.cookie, db_ret.cookie);
|
|
|
|
/* update the cookie to newly read cookie from GuC */
|
|
db_cmp.cookie = db_ret.cookie;
|
|
db_exc.cookie = db_ret.cookie + 1;
|
|
if (db_exc.cookie == 0)
|
|
db_exc.cookie = 1;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* __i915_guc_submit() - Submit commands through GuC
|
|
* @rq: request associated with the commands
|
|
*
|
|
* The caller must have already called i915_guc_wq_reserve() above with
|
|
* a result of 0 (success), guaranteeing that there is space in the work
|
|
* queue for the new request, so enqueuing the item cannot fail.
|
|
*
|
|
* Bad Things Will Happen if the caller violates this protocol e.g. calls
|
|
* submit() when _reserve() says there's no space, or calls _submit()
|
|
* a different number of times from (successful) calls to _reserve().
|
|
*
|
|
* The only error here arises if the doorbell hardware isn't functioning
|
|
* as expected, which really shouln't happen.
|
|
*/
|
|
static void __i915_guc_submit(struct drm_i915_gem_request *rq)
|
|
{
|
|
struct drm_i915_private *dev_priv = rq->i915;
|
|
struct intel_engine_cs *engine = rq->engine;
|
|
unsigned int engine_id = engine->id;
|
|
struct intel_guc *guc = &rq->i915->guc;
|
|
struct i915_guc_client *client = guc->execbuf_client;
|
|
unsigned long flags;
|
|
int b_ret;
|
|
|
|
/* WA to flush out the pending GMADR writes to ring buffer. */
|
|
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
|
|
POSTING_READ_FW(GUC_STATUS);
|
|
|
|
spin_lock_irqsave(&client->wq_lock, flags);
|
|
|
|
guc_wq_item_append(client, rq);
|
|
b_ret = guc_ring_doorbell(client);
|
|
|
|
client->submissions[engine_id] += 1;
|
|
client->retcode = b_ret;
|
|
if (b_ret)
|
|
client->b_fail += 1;
|
|
|
|
guc->submissions[engine_id] += 1;
|
|
guc->last_seqno[engine_id] = rq->global_seqno;
|
|
|
|
spin_unlock_irqrestore(&client->wq_lock, flags);
|
|
}
|
|
|
|
static void i915_guc_submit(struct drm_i915_gem_request *rq)
|
|
{
|
|
__i915_gem_request_submit(rq);
|
|
__i915_guc_submit(rq);
|
|
}
|
|
|
|
static void nested_enable_signaling(struct drm_i915_gem_request *rq)
|
|
{
|
|
/* If we use dma_fence_enable_sw_signaling() directly, lockdep
|
|
* detects an ordering issue between the fence lockclass and the
|
|
* global_timeline. This circular dependency can only occur via 2
|
|
* different fences (but same fence lockclass), so we use the nesting
|
|
* annotation here to prevent the warn, equivalent to the nesting
|
|
* inside i915_gem_request_submit() for when we also enable the
|
|
* signaler.
|
|
*/
|
|
|
|
if (test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
|
|
&rq->fence.flags))
|
|
return;
|
|
|
|
GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags));
|
|
trace_dma_fence_enable_signal(&rq->fence);
|
|
|
|
spin_lock_nested(&rq->lock, SINGLE_DEPTH_NESTING);
|
|
intel_engine_enable_signaling(rq);
|
|
spin_unlock(&rq->lock);
|
|
}
|
|
|
|
static bool i915_guc_dequeue(struct intel_engine_cs *engine)
|
|
{
|
|
struct execlist_port *port = engine->execlist_port;
|
|
struct drm_i915_gem_request *last = port[0].request;
|
|
unsigned long flags;
|
|
struct rb_node *rb;
|
|
bool submit = false;
|
|
|
|
/* After execlist_first is updated, the tasklet will be rescheduled.
|
|
*
|
|
* If we are currently running (inside the tasklet) and a third
|
|
* party queues a request and so updates engine->execlist_first under
|
|
* the spinlock (which we have elided), it will atomically set the
|
|
* TASKLET_SCHED flag causing the us to be re-executed and pick up
|
|
* the change in state (the update to TASKLET_SCHED incurs a memory
|
|
* barrier making this cross-cpu checking safe).
|
|
*/
|
|
if (!READ_ONCE(engine->execlist_first))
|
|
return false;
|
|
|
|
spin_lock_irqsave(&engine->timeline->lock, flags);
|
|
rb = engine->execlist_first;
|
|
while (rb) {
|
|
struct drm_i915_gem_request *rq =
|
|
rb_entry(rb, typeof(*rq), priotree.node);
|
|
|
|
if (last && rq->ctx != last->ctx) {
|
|
if (port != engine->execlist_port)
|
|
break;
|
|
|
|
i915_gem_request_assign(&port->request, last);
|
|
nested_enable_signaling(last);
|
|
port++;
|
|
}
|
|
|
|
rb = rb_next(rb);
|
|
rb_erase(&rq->priotree.node, &engine->execlist_queue);
|
|
RB_CLEAR_NODE(&rq->priotree.node);
|
|
rq->priotree.priority = INT_MAX;
|
|
|
|
trace_i915_gem_request_in(rq, port - engine->execlist_port);
|
|
i915_guc_submit(rq);
|
|
last = rq;
|
|
submit = true;
|
|
}
|
|
if (submit) {
|
|
i915_gem_request_assign(&port->request, last);
|
|
nested_enable_signaling(last);
|
|
engine->execlist_first = rb;
|
|
}
|
|
spin_unlock_irqrestore(&engine->timeline->lock, flags);
|
|
|
|
return submit;
|
|
}
|
|
|
|
static void i915_guc_irq_handler(unsigned long data)
|
|
{
|
|
struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
|
|
struct execlist_port *port = engine->execlist_port;
|
|
struct drm_i915_gem_request *rq;
|
|
bool submit;
|
|
|
|
do {
|
|
rq = port[0].request;
|
|
while (rq && i915_gem_request_completed(rq)) {
|
|
trace_i915_gem_request_out(rq);
|
|
i915_gem_request_put(rq);
|
|
port[0].request = port[1].request;
|
|
port[1].request = NULL;
|
|
rq = port[0].request;
|
|
}
|
|
|
|
submit = false;
|
|
if (!port[1].request)
|
|
submit = i915_guc_dequeue(engine);
|
|
} while (submit);
|
|
}
|
|
|
|
/*
|
|
* Everything below here is concerned with setup & teardown, and is
|
|
* therefore not part of the somewhat time-critical batch-submission
|
|
* path of i915_guc_submit() above.
|
|
*/
|
|
|
|
/**
|
|
* intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
|
|
* @guc: the guc
|
|
* @size: size of area to allocate (both virtual space and memory)
|
|
*
|
|
* This is a wrapper to create an object for use with the GuC. In order to
|
|
* use it inside the GuC, an object needs to be pinned lifetime, so we allocate
|
|
* both some backing storage and a range inside the Global GTT. We must pin
|
|
* it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
|
|
* range is reserved inside GuC.
|
|
*
|
|
* Return: A i915_vma if successful, otherwise an ERR_PTR.
|
|
*/
|
|
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
|
|
{
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
struct drm_i915_gem_object *obj;
|
|
struct i915_vma *vma;
|
|
int ret;
|
|
|
|
obj = i915_gem_object_create(dev_priv, size);
|
|
if (IS_ERR(obj))
|
|
return ERR_CAST(obj);
|
|
|
|
vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
|
|
if (IS_ERR(vma))
|
|
goto err;
|
|
|
|
ret = i915_vma_pin(vma, 0, PAGE_SIZE,
|
|
PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
|
|
if (ret) {
|
|
vma = ERR_PTR(ret);
|
|
goto err;
|
|
}
|
|
|
|
return vma;
|
|
|
|
err:
|
|
i915_gem_object_put(obj);
|
|
return vma;
|
|
}
|
|
|
|
static void
|
|
guc_client_free(struct drm_i915_private *dev_priv,
|
|
struct i915_guc_client *client)
|
|
{
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
if (!client)
|
|
return;
|
|
|
|
/*
|
|
* XXX: wait for any outstanding submissions before freeing memory.
|
|
* Be sure to drop any locks
|
|
*/
|
|
|
|
if (client->vaddr) {
|
|
/*
|
|
* If we got as far as setting up a doorbell, make sure we
|
|
* shut it down before unmapping & deallocating the memory.
|
|
*/
|
|
guc_disable_doorbell(guc, client);
|
|
|
|
i915_gem_object_unpin_map(client->vma->obj);
|
|
}
|
|
|
|
i915_vma_unpin_and_release(&client->vma);
|
|
|
|
if (client->ctx_index != GUC_INVALID_CTX_ID) {
|
|
guc_ctx_desc_fini(guc, client);
|
|
ida_simple_remove(&guc->ctx_ids, client->ctx_index);
|
|
}
|
|
|
|
kfree(client);
|
|
}
|
|
|
|
/* Check that a doorbell register is in the expected state */
|
|
static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id)
|
|
{
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
i915_reg_t drbreg = GEN8_DRBREGL(db_id);
|
|
uint32_t value = I915_READ(drbreg);
|
|
bool enabled = (value & GUC_DOORBELL_ENABLED) != 0;
|
|
bool expected = test_bit(db_id, guc->doorbell_bitmap);
|
|
|
|
if (enabled == expected)
|
|
return true;
|
|
|
|
DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n",
|
|
db_id, drbreg.reg, value,
|
|
expected ? "active" : "inactive");
|
|
|
|
return false;
|
|
}
|
|
|
|
/*
|
|
* Borrow the first client to set up & tear down each unused doorbell
|
|
* in turn, to ensure that all doorbell h/w is (re)initialised.
|
|
*/
|
|
static void guc_init_doorbell_hw(struct intel_guc *guc)
|
|
{
|
|
struct i915_guc_client *client = guc->execbuf_client;
|
|
uint16_t db_id;
|
|
int i, err;
|
|
|
|
guc_disable_doorbell(guc, client);
|
|
|
|
for (i = 0; i < GUC_MAX_DOORBELLS; ++i) {
|
|
/* Skip if doorbell is OK */
|
|
if (guc_doorbell_check(guc, i))
|
|
continue;
|
|
|
|
err = guc_update_doorbell_id(guc, client, i);
|
|
if (err)
|
|
DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n",
|
|
i, err);
|
|
}
|
|
|
|
db_id = select_doorbell_register(guc, client->priority);
|
|
WARN_ON(db_id == GUC_INVALID_DOORBELL_ID);
|
|
|
|
err = guc_update_doorbell_id(guc, client, db_id);
|
|
if (err)
|
|
DRM_WARN("Failed to restore doorbell to %d, err %d\n",
|
|
db_id, err);
|
|
|
|
/* Read back & verify all doorbell registers */
|
|
for (i = 0; i < GUC_MAX_DOORBELLS; ++i)
|
|
(void)guc_doorbell_check(guc, i);
|
|
}
|
|
|
|
/**
|
|
* guc_client_alloc() - Allocate an i915_guc_client
|
|
* @dev_priv: driver private data structure
|
|
* @engines: The set of engines to enable for this client
|
|
* @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
|
|
* The kernel client to replace ExecList submission is created with
|
|
* NORMAL priority. Priority of a client for scheduler can be HIGH,
|
|
* while a preemption context can use CRITICAL.
|
|
* @ctx: the context that owns the client (we use the default render
|
|
* context)
|
|
*
|
|
* Return: An i915_guc_client object if success, else NULL.
|
|
*/
|
|
static struct i915_guc_client *
|
|
guc_client_alloc(struct drm_i915_private *dev_priv,
|
|
uint32_t engines,
|
|
uint32_t priority,
|
|
struct i915_gem_context *ctx)
|
|
{
|
|
struct i915_guc_client *client;
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
struct i915_vma *vma;
|
|
void *vaddr;
|
|
uint16_t db_id;
|
|
|
|
client = kzalloc(sizeof(*client), GFP_KERNEL);
|
|
if (!client)
|
|
return NULL;
|
|
|
|
client->owner = ctx;
|
|
client->guc = guc;
|
|
client->engines = engines;
|
|
client->priority = priority;
|
|
client->doorbell_id = GUC_INVALID_DOORBELL_ID;
|
|
|
|
client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
|
|
GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
|
|
if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
|
|
client->ctx_index = GUC_INVALID_CTX_ID;
|
|
goto err;
|
|
}
|
|
|
|
/* The first page is doorbell/proc_desc. Two followed pages are wq. */
|
|
vma = intel_guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
|
|
if (IS_ERR(vma))
|
|
goto err;
|
|
|
|
/* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
|
|
client->vma = vma;
|
|
|
|
vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
|
|
if (IS_ERR(vaddr))
|
|
goto err;
|
|
|
|
client->vaddr = vaddr;
|
|
|
|
spin_lock_init(&client->wq_lock);
|
|
client->wq_offset = GUC_DB_SIZE;
|
|
client->wq_size = GUC_WQ_SIZE;
|
|
|
|
db_id = select_doorbell_register(guc, client->priority);
|
|
if (db_id == GUC_INVALID_DOORBELL_ID)
|
|
/* XXX: evict a doorbell instead? */
|
|
goto err;
|
|
|
|
client->doorbell_offset = select_doorbell_cacheline(guc);
|
|
|
|
/*
|
|
* Since the doorbell only requires a single cacheline, we can save
|
|
* space by putting the application process descriptor in the same
|
|
* page. Use the half of the page that doesn't include the doorbell.
|
|
*/
|
|
if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
|
|
client->proc_desc_offset = 0;
|
|
else
|
|
client->proc_desc_offset = (GUC_DB_SIZE / 2);
|
|
|
|
guc_proc_desc_init(guc, client);
|
|
guc_ctx_desc_init(guc, client);
|
|
|
|
/* For runtime client allocation we need to enable the doorbell. Not
|
|
* required yet for the static execbuf_client as this special kernel
|
|
* client is enabled from i915_guc_submission_enable().
|
|
*
|
|
* guc_update_doorbell_id(guc, client, db_id);
|
|
*/
|
|
|
|
DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n",
|
|
priority, client, client->engines, client->ctx_index);
|
|
DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n",
|
|
client->doorbell_id, client->doorbell_offset);
|
|
|
|
return client;
|
|
|
|
err:
|
|
guc_client_free(dev_priv, client);
|
|
return NULL;
|
|
}
|
|
|
|
|
|
|
|
static void guc_policies_init(struct guc_policies *policies)
|
|
{
|
|
struct guc_policy *policy;
|
|
u32 p, i;
|
|
|
|
policies->dpc_promote_time = 500000;
|
|
policies->max_num_work_items = POLICY_MAX_NUM_WI;
|
|
|
|
for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
|
|
for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
|
|
policy = &policies->policy[p][i];
|
|
|
|
policy->execution_quantum = 1000000;
|
|
policy->preemption_time = 500000;
|
|
policy->fault_time = 250000;
|
|
policy->policy_flags = 0;
|
|
}
|
|
}
|
|
|
|
policies->is_valid = 1;
|
|
}
|
|
|
|
static void guc_addon_create(struct intel_guc *guc)
|
|
{
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
struct i915_vma *vma;
|
|
struct page *page;
|
|
/* The ads obj includes the struct itself and buffers passed to GuC */
|
|
struct {
|
|
struct guc_ads ads;
|
|
struct guc_policies policies;
|
|
struct guc_mmio_reg_state reg_state;
|
|
u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
|
|
} __packed *blob;
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
u32 base;
|
|
|
|
vma = guc->ads_vma;
|
|
if (!vma) {
|
|
vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
|
|
if (IS_ERR(vma))
|
|
return;
|
|
|
|
guc->ads_vma = vma;
|
|
}
|
|
|
|
page = i915_vma_first_page(vma);
|
|
blob = kmap(page);
|
|
|
|
/* GuC scheduling policies */
|
|
guc_policies_init(&blob->policies);
|
|
|
|
/* MMIO reg state */
|
|
for_each_engine(engine, dev_priv, id) {
|
|
blob->reg_state.mmio_white_list[engine->guc_id].mmio_start =
|
|
engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
|
|
|
|
/* Nothing to be saved or restored for now. */
|
|
blob->reg_state.mmio_white_list[engine->guc_id].count = 0;
|
|
}
|
|
|
|
/*
|
|
* The GuC requires a "Golden Context" when it reinitialises
|
|
* engines after a reset. Here we use the Render ring default
|
|
* context, which must already exist and be pinned in the GGTT,
|
|
* so its address won't change after we've told the GuC where
|
|
* to find it.
|
|
*/
|
|
blob->ads.golden_context_lrca =
|
|
dev_priv->engine[RCS]->status_page.ggtt_offset;
|
|
|
|
for_each_engine(engine, dev_priv, id)
|
|
blob->ads.eng_state_size[engine->guc_id] =
|
|
intel_lr_context_size(engine);
|
|
|
|
base = guc_ggtt_offset(vma);
|
|
blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
|
|
blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
|
|
blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
|
|
|
|
kunmap(page);
|
|
}
|
|
|
|
/*
|
|
* Set up the memory resources to be shared with the GuC. At this point,
|
|
* we require just one object that can be mapped through the GGTT.
|
|
*/
|
|
int i915_guc_submission_init(struct drm_i915_private *dev_priv)
|
|
{
|
|
const size_t ctxsize = sizeof(struct guc_context_desc);
|
|
const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
|
|
const size_t gemsize = round_up(poolsize, PAGE_SIZE);
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
struct i915_vma *vma;
|
|
|
|
if (!HAS_GUC_SCHED(dev_priv))
|
|
return 0;
|
|
|
|
/* Wipe bitmap & delete client in case of reinitialisation */
|
|
bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS);
|
|
i915_guc_submission_disable(dev_priv);
|
|
|
|
if (!i915.enable_guc_submission)
|
|
return 0; /* not enabled */
|
|
|
|
if (guc->ctx_pool_vma)
|
|
return 0; /* already allocated */
|
|
|
|
vma = intel_guc_allocate_vma(guc, gemsize);
|
|
if (IS_ERR(vma))
|
|
return PTR_ERR(vma);
|
|
|
|
guc->ctx_pool_vma = vma;
|
|
ida_init(&guc->ctx_ids);
|
|
intel_guc_log_create(guc);
|
|
guc_addon_create(guc);
|
|
|
|
guc->execbuf_client = guc_client_alloc(dev_priv,
|
|
INTEL_INFO(dev_priv)->ring_mask,
|
|
GUC_CTX_PRIORITY_KMD_NORMAL,
|
|
dev_priv->kernel_context);
|
|
if (!guc->execbuf_client) {
|
|
DRM_ERROR("Failed to create GuC client for execbuf!\n");
|
|
goto err;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err:
|
|
i915_guc_submission_fini(dev_priv);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static void guc_reset_wq(struct i915_guc_client *client)
|
|
{
|
|
struct guc_process_desc *desc = client->vaddr +
|
|
client->proc_desc_offset;
|
|
|
|
desc->head = 0;
|
|
desc->tail = 0;
|
|
|
|
client->wq_tail = 0;
|
|
}
|
|
|
|
static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
int irqs;
|
|
|
|
/* tell all command streamers to forward interrupts (but not vblank) to GuC */
|
|
irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
|
|
for_each_engine(engine, dev_priv, id)
|
|
I915_WRITE(RING_MODE_GEN7(engine), irqs);
|
|
|
|
/* route USER_INTERRUPT to Host, all others are sent to GuC. */
|
|
irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
|
|
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
|
|
/* These three registers have the same bit definitions */
|
|
I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
|
|
I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
|
|
I915_WRITE(GUC_WD_VECS_IER, ~irqs);
|
|
|
|
/*
|
|
* The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
|
|
* (unmasked) PM interrupts to the GuC. All other bits of this
|
|
* register *disable* generation of a specific interrupt.
|
|
*
|
|
* 'pm_intrmsk_mbz' indicates bits that are NOT to be set when
|
|
* writing to the PM interrupt mask register, i.e. interrupts
|
|
* that must not be disabled.
|
|
*
|
|
* If the GuC is handling these interrupts, then we must not let
|
|
* the PM code disable ANY interrupt that the GuC is expecting.
|
|
* So for each ENABLED (0) bit in this register, we must SET the
|
|
* bit in pm_intrmsk_mbz so that it's left enabled for the GuC.
|
|
* GuC needs ARAT expired interrupt unmasked hence it is set in
|
|
* pm_intrmsk_mbz.
|
|
*
|
|
* Here we CLEAR REDIRECT_TO_GUC bit in pm_intrmsk_mbz, which will
|
|
* result in the register bit being left SET!
|
|
*/
|
|
dev_priv->rps.pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
|
|
dev_priv->rps.pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
|
|
}
|
|
|
|
int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
struct i915_guc_client *client = guc->execbuf_client;
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
|
|
if (!client)
|
|
return -ENODEV;
|
|
|
|
intel_guc_sample_forcewake(guc);
|
|
|
|
guc_reset_wq(client);
|
|
guc_init_doorbell_hw(guc);
|
|
|
|
/* Take over from manual control of ELSP (execlists) */
|
|
guc_interrupts_capture(dev_priv);
|
|
|
|
for_each_engine(engine, dev_priv, id) {
|
|
const int wqi_size = sizeof(struct guc_wq_item);
|
|
struct drm_i915_gem_request *rq;
|
|
|
|
/* The tasklet was initialised by execlists, and may be in
|
|
* a state of flux (across a reset) and so we just want to
|
|
* take over the callback without changing any other state
|
|
* in the tasklet.
|
|
*/
|
|
engine->irq_tasklet.func = i915_guc_irq_handler;
|
|
clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
|
|
|
|
/* Replay the current set of previously submitted requests */
|
|
spin_lock_irq(&engine->timeline->lock);
|
|
list_for_each_entry(rq, &engine->timeline->requests, link) {
|
|
guc_client_update_wq_rsvd(client, wqi_size);
|
|
__i915_guc_submit(rq);
|
|
}
|
|
spin_unlock_irq(&engine->timeline->lock);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void guc_interrupts_release(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
int irqs;
|
|
|
|
/*
|
|
* tell all command streamers NOT to forward interrupts or vblank
|
|
* to GuC.
|
|
*/
|
|
irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
|
|
irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
|
|
for_each_engine(engine, dev_priv, id)
|
|
I915_WRITE(RING_MODE_GEN7(engine), irqs);
|
|
|
|
/* route all GT interrupts to the host */
|
|
I915_WRITE(GUC_BCS_RCS_IER, 0);
|
|
I915_WRITE(GUC_VCS2_VCS1_IER, 0);
|
|
I915_WRITE(GUC_WD_VECS_IER, 0);
|
|
|
|
dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
|
|
dev_priv->rps.pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
|
|
}
|
|
|
|
void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
guc_interrupts_release(dev_priv);
|
|
|
|
if (!guc->execbuf_client)
|
|
return;
|
|
|
|
/* Revert back to manual ELSP submission */
|
|
intel_engines_reset_default_submission(dev_priv);
|
|
}
|
|
|
|
void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
struct i915_guc_client *client;
|
|
|
|
client = fetch_and_zero(&guc->execbuf_client);
|
|
if (!client)
|
|
return;
|
|
|
|
guc_client_free(dev_priv, client);
|
|
|
|
i915_vma_unpin_and_release(&guc->ads_vma);
|
|
i915_vma_unpin_and_release(&guc->log.vma);
|
|
|
|
if (guc->ctx_pool_vma)
|
|
ida_destroy(&guc->ctx_ids);
|
|
i915_vma_unpin_and_release(&guc->ctx_pool_vma);
|
|
}
|
|
|
|
/**
|
|
* intel_guc_suspend() - notify GuC entering suspend state
|
|
* @dev_priv: i915 device private
|
|
*/
|
|
int intel_guc_suspend(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
struct i915_gem_context *ctx;
|
|
u32 data[3];
|
|
|
|
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
|
|
return 0;
|
|
|
|
gen9_disable_guc_interrupts(dev_priv);
|
|
|
|
ctx = dev_priv->kernel_context;
|
|
|
|
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
|
|
/* any value greater than GUC_POWER_D0 */
|
|
data[1] = GUC_POWER_D1;
|
|
/* first page is shared data with GuC */
|
|
data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
|
|
|
|
return intel_guc_send(guc, data, ARRAY_SIZE(data));
|
|
}
|
|
|
|
|
|
/**
|
|
* intel_guc_resume() - notify GuC resuming from suspend state
|
|
* @dev_priv: i915 device private
|
|
*/
|
|
int intel_guc_resume(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
struct i915_gem_context *ctx;
|
|
u32 data[3];
|
|
|
|
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
|
|
return 0;
|
|
|
|
if (i915.guc_log_level >= 0)
|
|
gen9_enable_guc_interrupts(dev_priv);
|
|
|
|
ctx = dev_priv->kernel_context;
|
|
|
|
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
|
|
data[1] = GUC_POWER_D0;
|
|
/* first page is shared data with GuC */
|
|
data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
|
|
|
|
return intel_guc_send(guc, data, ARRAY_SIZE(data));
|
|
}
|
|
|
|
|