319 lines
8.7 KiB
C
319 lines
8.7 KiB
C
/*
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* Copyright © 2008-2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "intel_drv.h"
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static void
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intel_dp_dump_link_status(const uint8_t link_status[DP_LINK_STATUS_SIZE])
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{
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DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
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link_status[0], link_status[1], link_status[2],
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link_status[3], link_status[4], link_status[5]);
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}
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static void
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intel_get_adjust_train(struct intel_dp *intel_dp,
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const uint8_t link_status[DP_LINK_STATUS_SIZE])
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{
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uint8_t v = 0;
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uint8_t p = 0;
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int lane;
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uint8_t voltage_max;
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uint8_t preemph_max;
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for (lane = 0; lane < intel_dp->lane_count; lane++) {
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uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
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uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
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if (this_v > v)
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v = this_v;
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if (this_p > p)
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p = this_p;
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}
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voltage_max = intel_dp_voltage_max(intel_dp);
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if (v >= voltage_max)
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v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
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preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
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if (p >= preemph_max)
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p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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for (lane = 0; lane < 4; lane++)
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intel_dp->train_set[lane] = v | p;
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}
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static bool
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intel_dp_set_link_train(struct intel_dp *intel_dp,
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uint8_t dp_train_pat)
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{
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uint8_t buf[sizeof(intel_dp->train_set) + 1];
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int ret, len;
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intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
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buf[0] = dp_train_pat;
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if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
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DP_TRAINING_PATTERN_DISABLE) {
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/* don't write DP_TRAINING_LANEx_SET on disable */
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len = 1;
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} else {
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/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
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memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
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len = intel_dp->lane_count + 1;
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}
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ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
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buf, len);
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return ret == len;
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}
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static bool
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intel_dp_reset_link_train(struct intel_dp *intel_dp,
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uint8_t dp_train_pat)
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{
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memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
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intel_dp_set_signal_levels(intel_dp);
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return intel_dp_set_link_train(intel_dp, dp_train_pat);
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}
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static bool
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intel_dp_update_link_train(struct intel_dp *intel_dp)
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{
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int ret;
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intel_dp_set_signal_levels(intel_dp);
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ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
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intel_dp->train_set, intel_dp->lane_count);
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return ret == intel_dp->lane_count;
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}
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static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
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{
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int lane;
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for (lane = 0; lane < intel_dp->lane_count; lane++)
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if ((intel_dp->train_set[lane] &
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DP_TRAIN_MAX_SWING_REACHED) == 0)
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return false;
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return true;
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}
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/* Enable corresponding port and start training pattern 1 */
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static bool
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intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
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{
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uint8_t voltage;
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int voltage_tries, max_vswing_tries;
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uint8_t link_config[2];
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uint8_t link_bw, rate_select;
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if (intel_dp->prepare_link_retrain)
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intel_dp->prepare_link_retrain(intel_dp);
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intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
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&link_bw, &rate_select);
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/* Write the link configuration data */
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link_config[0] = link_bw;
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link_config[1] = intel_dp->lane_count;
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if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
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link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
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if (intel_dp->num_sink_rates)
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drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
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&rate_select, 1);
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link_config[0] = 0;
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link_config[1] = DP_SET_ANSI_8B10B;
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drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
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intel_dp->DP |= DP_PORT_EN;
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/* clock recovery */
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if (!intel_dp_reset_link_train(intel_dp,
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DP_TRAINING_PATTERN_1 |
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DP_LINK_SCRAMBLING_DISABLE)) {
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DRM_ERROR("failed to enable link training\n");
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return false;
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}
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voltage_tries = 1;
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max_vswing_tries = 0;
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for (;;) {
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uint8_t link_status[DP_LINK_STATUS_SIZE];
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drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
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if (!intel_dp_get_link_status(intel_dp, link_status)) {
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DRM_ERROR("failed to get link status\n");
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return false;
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}
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if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
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DRM_DEBUG_KMS("clock recovery OK\n");
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return true;
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}
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if (voltage_tries == 5) {
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DRM_DEBUG_KMS("Same voltage tried 5 times\n");
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return false;
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}
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if (max_vswing_tries == 1) {
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DRM_DEBUG_KMS("Max Voltage Swing reached\n");
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return false;
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}
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voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
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/* Update training set as requested by target */
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intel_get_adjust_train(intel_dp, link_status);
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if (!intel_dp_update_link_train(intel_dp)) {
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DRM_ERROR("failed to update link training\n");
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return false;
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}
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if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
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voltage)
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++voltage_tries;
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else
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voltage_tries = 1;
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if (intel_dp_link_max_vswing_reached(intel_dp))
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++max_vswing_tries;
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}
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}
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/*
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* Pick training pattern for channel equalization. Training Pattern 3 for HBR2
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* or 1.2 devices that support it, Training Pattern 2 otherwise.
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*/
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static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
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{
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u32 training_pattern = DP_TRAINING_PATTERN_2;
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bool source_tps3, sink_tps3;
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/*
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* Intel platforms that support HBR2 also support TPS3. TPS3 support is
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* also mandatory for downstream devices that support HBR2. However, not
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* all sinks follow the spec.
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*/
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source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
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sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
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if (source_tps3 && sink_tps3) {
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training_pattern = DP_TRAINING_PATTERN_3;
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} else if (intel_dp->link_rate == 540000) {
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if (!source_tps3)
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DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n");
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if (!sink_tps3)
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DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
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}
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return training_pattern;
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}
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static bool
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intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
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{
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int tries;
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u32 training_pattern;
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uint8_t link_status[DP_LINK_STATUS_SIZE];
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training_pattern = intel_dp_training_pattern(intel_dp);
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/* channel equalization */
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if (!intel_dp_set_link_train(intel_dp,
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training_pattern |
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DP_LINK_SCRAMBLING_DISABLE)) {
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DRM_ERROR("failed to start channel equalization\n");
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return false;
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}
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intel_dp->channel_eq_status = false;
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for (tries = 0; tries < 5; tries++) {
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drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
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if (!intel_dp_get_link_status(intel_dp, link_status)) {
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DRM_ERROR("failed to get link status\n");
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break;
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}
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/* Make sure clock is still ok */
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if (!drm_dp_clock_recovery_ok(link_status,
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intel_dp->lane_count)) {
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intel_dp_dump_link_status(link_status);
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DRM_DEBUG_KMS("Clock recovery check failed, cannot "
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"continue channel equalization\n");
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break;
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}
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if (drm_dp_channel_eq_ok(link_status,
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intel_dp->lane_count)) {
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intel_dp->channel_eq_status = true;
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DRM_DEBUG_KMS("Channel EQ done. DP Training "
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"successful\n");
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break;
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}
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/* Update training set as requested by target */
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intel_get_adjust_train(intel_dp, link_status);
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if (!intel_dp_update_link_train(intel_dp)) {
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DRM_ERROR("failed to update link training\n");
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break;
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}
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}
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/* Try 5 times, else fail and try at lower BW */
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if (tries == 5) {
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intel_dp_dump_link_status(link_status);
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DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
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}
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intel_dp_set_idle_link_train(intel_dp);
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return intel_dp->channel_eq_status;
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}
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void intel_dp_stop_link_train(struct intel_dp *intel_dp)
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{
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intel_dp_set_link_train(intel_dp,
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DP_TRAINING_PATTERN_DISABLE);
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}
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void
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intel_dp_start_link_train(struct intel_dp *intel_dp)
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{
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intel_dp_link_training_clock_recovery(intel_dp);
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intel_dp_link_training_channel_equalization(intel_dp);
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}
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