86 lines
2.6 KiB
C
86 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#define CLK_COUNT 4 /* cpu_clk, sys_clk, usb_clk, sdio_clk */
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static struct clk *clks[CLK_COUNT];
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static struct clk_onecell_data clk_data = { clks, CLK_COUNT };
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#define SYSCLK_DIV 0x20
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#define CPUCLK_DIV 0x24
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#define DIV_BYPASS BIT(23)
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/*** CLKGEN_PLL ***/
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#define extract_pll_n(val) ((val >> 0) & ((1u << 7) - 1))
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#define extract_pll_k(val) ((val >> 13) & ((1u << 3) - 1))
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#define extract_pll_m(val) ((val >> 16) & ((1u << 3) - 1))
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#define extract_pll_isel(val) ((val >> 24) & ((1u << 3) - 1))
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static void __init make_pll(int idx, const char *parent, void __iomem *base)
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{
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char name[8];
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u32 val, mul, div;
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sprintf(name, "pll%d", idx);
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val = readl(base + idx * 8);
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mul = extract_pll_n(val) + 1;
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div = (extract_pll_m(val) + 1) << extract_pll_k(val);
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clk_register_fixed_factor(NULL, name, parent, 0, mul, div);
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if (extract_pll_isel(val) != 1)
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panic("%s: input not set to XTAL_IN\n", name);
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}
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static void __init make_cd(int idx, void __iomem *base)
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{
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char name[8];
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u32 val, mul, div;
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sprintf(name, "cd%d", idx);
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val = readl(base + idx * 8);
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mul = 1 << 27;
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div = (2 << 27) + val;
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clk_register_fixed_factor(NULL, name, "pll2", 0, mul, div);
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if (val > 0xf0000000)
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panic("%s: unsupported divider %x\n", name, val);
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}
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static void __init tango4_clkgen_setup(struct device_node *np)
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{
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struct clk **pp = clk_data.clks;
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void __iomem *base = of_iomap(np, 0);
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const char *parent = of_clk_get_parent_name(np, 0);
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if (!base)
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panic("%pOFn: invalid address\n", np);
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if (readl(base + CPUCLK_DIV) & DIV_BYPASS)
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panic("%pOFn: unsupported cpuclk setup\n", np);
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if (readl(base + SYSCLK_DIV) & DIV_BYPASS)
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panic("%pOFn: unsupported sysclk setup\n", np);
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writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */
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make_pll(0, parent, base);
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make_pll(1, parent, base);
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make_pll(2, parent, base);
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make_cd(2, base + 0x80);
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make_cd(6, base + 0x80);
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pp[0] = clk_register_divider(NULL, "cpu_clk", "pll0", 0,
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base + CPUCLK_DIV, 8, 8, CLK_DIVIDER_ONE_BASED, NULL);
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pp[1] = clk_register_fixed_factor(NULL, "sys_clk", "pll1", 0, 1, 4);
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pp[2] = clk_register_fixed_factor(NULL, "usb_clk", "cd2", 0, 1, 2);
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pp[3] = clk_register_fixed_factor(NULL, "sdio_clk", "cd6", 0, 1, 2);
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if (IS_ERR(pp[0]) || IS_ERR(pp[1]) || IS_ERR(pp[2]) || IS_ERR(pp[3]))
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panic("%pOFn: clk registration failed\n", np);
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if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data))
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panic("%pOFn: clk provider registration failed\n", np);
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}
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CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);
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