898 lines
23 KiB
C
898 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap-divider.h"
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#include "common.h"
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#include "gdsc.h"
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#include "reset.h"
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enum {
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P_BI_TCXO,
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P_CORE_BI_PLL_TEST_SE,
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P_DISP_CC_PLL0_OUT_MAIN,
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P_DSI0_PHY_PLL_OUT_BYTECLK,
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P_DSI0_PHY_PLL_OUT_DSICLK,
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P_DSI1_PHY_PLL_OUT_BYTECLK,
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P_DSI1_PHY_PLL_OUT_DSICLK,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_DP_PHY_PLL_LINK_CLK,
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P_DP_PHY_PLL_VCO_DIV_CLK,
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};
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static const struct parent_map disp_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
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{ P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const disp_cc_parent_names_0[] = {
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"bi_tcxo",
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"dsi0_phy_pll_out_byteclk",
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"dsi1_phy_pll_out_byteclk",
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"core_bi_pll_test_se",
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};
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static const struct parent_map disp_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_DP_PHY_PLL_LINK_CLK, 1 },
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{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const disp_cc_parent_names_1[] = {
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"bi_tcxo",
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"dp_link_clk_divsel_ten",
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"dp_vco_divided_clk_src_mux",
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"core_bi_pll_test_se",
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};
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static const struct parent_map disp_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const disp_cc_parent_names_2[] = {
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"bi_tcxo",
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"core_bi_pll_test_se",
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};
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static const struct parent_map disp_cc_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPLL0_OUT_MAIN, 4 },
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{ P_GPLL0_OUT_MAIN_DIV, 5 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const disp_cc_parent_names_3[] = {
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"bi_tcxo",
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"disp_cc_pll0",
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"gcc_disp_gpll0_clk_src",
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"gcc_disp_gpll0_div_clk_src",
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"core_bi_pll_test_se",
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};
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static const struct parent_map disp_cc_parent_map_4[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
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{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const disp_cc_parent_names_4[] = {
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"bi_tcxo",
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"dsi0_phy_pll_out_dsiclk",
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"dsi1_phy_pll_out_dsiclk",
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"core_bi_pll_test_se",
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};
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static struct clk_alpha_pll disp_cc_pll0 = {
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.offset = 0x0,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_pll0",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_fabia_ops,
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},
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},
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};
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/* Return the HW recalc rate for idle use case */
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static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
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.cmd_rcgr = 0x20d0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_clk_src",
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.parent_names = disp_cc_parent_names_0,
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.num_parents = 4,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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};
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/* Return the HW recalc rate for idle use case */
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static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
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.cmd_rcgr = 0x20ec,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte1_clk_src",
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.parent_names = disp_cc_parent_names_0,
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.num_parents = 4,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
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.cmd_rcgr = 0x219c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_2,
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.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_aux_clk_src",
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.parent_names = disp_cc_parent_names_2,
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
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.cmd_rcgr = 0x2154,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_1,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_crypto_clk_src",
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.parent_names = disp_cc_parent_names_1,
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.num_parents = 4,
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.ops = &clk_byte2_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
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.cmd_rcgr = 0x2138,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_1,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_link_clk_src",
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.parent_names = disp_cc_parent_names_1,
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.num_parents = 4,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
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.cmd_rcgr = 0x2184,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_1,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_pixel1_clk_src",
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.parent_names = disp_cc_parent_names_1,
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.num_parents = 4,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_dp_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
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.cmd_rcgr = 0x216c,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_1,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_pixel_clk_src",
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.parent_names = disp_cc_parent_names_1,
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.num_parents = 4,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_dp_ops,
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
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.cmd_rcgr = 0x2108,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_esc0_clk_src",
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.parent_names = disp_cc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
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.cmd_rcgr = 0x2120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_esc1_clk_src",
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.parent_names = disp_cc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_ops,
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(85714286, P_GPLL0_OUT_MAIN, 7, 0, 0),
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F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
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F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
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F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
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F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
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F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
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F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
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.cmd_rcgr = 0x2088,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_3,
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.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_mdp_clk_src",
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.parent_names = disp_cc_parent_names_3,
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.num_parents = 5,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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/* Return the HW recalc rate for idle use case */
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static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
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.cmd_rcgr = 0x2058,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_4,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_pclk0_clk_src",
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.parent_names = disp_cc_parent_names_4,
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.num_parents = 4,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_pixel_ops,
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},
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};
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/* Return the HW recalc rate for idle use case */
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static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
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.cmd_rcgr = 0x2070,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_4,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_pclk1_clk_src",
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.parent_names = disp_cc_parent_names_4,
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.num_parents = 4,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_pixel_ops,
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
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F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
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F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
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F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
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.cmd_rcgr = 0x20a0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_3,
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.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_rot_clk_src",
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.parent_names = disp_cc_parent_names_3,
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.num_parents = 5,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
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.cmd_rcgr = 0x20b8,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_2,
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.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_vsync_clk_src",
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.parent_names = disp_cc_parent_names_2,
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.num_parents = 2,
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_branch disp_cc_mdss_ahb_clk = {
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.halt_reg = 0x4004,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x4004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_ahb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_axi_clk = {
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.halt_reg = 0x4008,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x4008,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_axi_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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/* Return the HW recalc rate for idle use case */
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static struct clk_branch disp_cc_mdss_byte0_clk = {
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.halt_reg = 0x2028,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x2028,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_clk",
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.parent_names = (const char *[]){
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"disp_cc_mdss_byte0_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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/* Return the HW recalc rate for idle use case */
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static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
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.reg = 0x20e8,
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.shift = 0,
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.width = 2,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_div_clk_src",
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.parent_names = (const char *[]){
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"disp_cc_mdss_byte0_clk_src",
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},
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.num_parents = 1,
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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/* Return the HW recalc rate for idle use case */
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static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
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.halt_reg = 0x202c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x202c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_intf_clk",
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.parent_names = (const char *[]){
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"disp_cc_mdss_byte0_div_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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/* Return the HW recalc rate for idle use case */
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static struct clk_branch disp_cc_mdss_byte1_clk = {
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.halt_reg = 0x2030,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x2030,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte1_clk",
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.parent_names = (const char *[]){
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"disp_cc_mdss_byte1_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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/* Return the HW recalc rate for idle use case */
|
|
static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
|
|
.reg = 0x2104,
|
|
.shift = 0,
|
|
.width = 2,
|
|
.clkr = {
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_byte1_div_clk_src",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_byte1_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_regmap_div_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* Return the HW recalc rate for idle use case */
|
|
static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
|
|
.halt_reg = 0x2034,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2034,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_byte1_intf_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_byte1_div_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dp_aux_clk = {
|
|
.halt_reg = 0x2054,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2054,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_dp_aux_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_dp_aux_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
|
|
.halt_reg = 0x2048,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2048,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_dp_crypto_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_dp_crypto_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dp_link_clk = {
|
|
.halt_reg = 0x2040,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2040,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_dp_link_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_dp_link_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */
|
|
static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
|
|
.halt_reg = 0x2044,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2044,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_dp_link_intf_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_dp_link_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
|
|
.halt_reg = 0x2050,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2050,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_dp_pixel1_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_dp_pixel1_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
|
|
.halt_reg = 0x204c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x204c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_dp_pixel_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_dp_pixel_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_esc0_clk = {
|
|
.halt_reg = 0x2038,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2038,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_esc0_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_esc0_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_esc1_clk = {
|
|
.halt_reg = 0x203c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x203c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_esc1_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_esc1_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_mdp_clk = {
|
|
.halt_reg = 0x200c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x200c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_mdp_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_mdp_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
|
|
.halt_reg = 0x201c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x201c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_mdp_lut_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_mdp_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* Return the HW recalc rate for idle use case */
|
|
static struct clk_branch disp_cc_mdss_pclk0_clk = {
|
|
.halt_reg = 0x2004,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_pclk0_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_pclk0_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* Return the HW recalc rate for idle use case */
|
|
static struct clk_branch disp_cc_mdss_pclk1_clk = {
|
|
.halt_reg = 0x2008,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2008,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_pclk1_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_pclk1_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_rot_clk = {
|
|
.halt_reg = 0x2014,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2014,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_rot_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_rot_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
|
|
.halt_reg = 0x5004,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x5004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_rscc_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
|
|
.halt_reg = 0x5008,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x5008,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_rscc_vsync_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_vsync_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_vsync_clk = {
|
|
.halt_reg = 0x2024,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2024,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_vsync_clk",
|
|
.parent_names = (const char *[]){
|
|
"disp_cc_mdss_vsync_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct gdsc mdss_gdsc = {
|
|
.gdscr = 0x3000,
|
|
.pd = {
|
|
.name = "mdss_gdsc",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
.flags = HW_CTRL | POLL_CFG_GDSCR,
|
|
};
|
|
|
|
static struct clk_regmap *disp_cc_sdm845_clocks[] = {
|
|
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_AXI_CLK] = &disp_cc_mdss_axi_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =
|
|
&disp_cc_mdss_byte0_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =
|
|
&disp_cc_mdss_byte1_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
|
|
[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
|
|
[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
|
|
[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] =
|
|
&disp_cc_mdss_dp_crypto_clk_src.clkr,
|
|
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
|
|
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
|
|
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
|
|
[DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] =
|
|
&disp_cc_mdss_dp_pixel1_clk_src.clkr,
|
|
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
|
|
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
|
|
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
|
|
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
|
|
[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
|
|
[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
|
|
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
|
|
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
|
|
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
|
|
[DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
|
|
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
|
|
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
|
|
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
|
|
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
|
|
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
|
|
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
|
|
};
|
|
|
|
static const struct qcom_reset_map disp_cc_sdm845_resets[] = {
|
|
[DISP_CC_MDSS_RSCC_BCR] = { 0x5000 },
|
|
};
|
|
|
|
static struct gdsc *disp_cc_sdm845_gdscs[] = {
|
|
[MDSS_GDSC] = &mdss_gdsc,
|
|
};
|
|
|
|
static const struct regmap_config disp_cc_sdm845_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0x10000,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static const struct qcom_cc_desc disp_cc_sdm845_desc = {
|
|
.config = &disp_cc_sdm845_regmap_config,
|
|
.clks = disp_cc_sdm845_clocks,
|
|
.num_clks = ARRAY_SIZE(disp_cc_sdm845_clocks),
|
|
.resets = disp_cc_sdm845_resets,
|
|
.num_resets = ARRAY_SIZE(disp_cc_sdm845_resets),
|
|
.gdscs = disp_cc_sdm845_gdscs,
|
|
.num_gdscs = ARRAY_SIZE(disp_cc_sdm845_gdscs),
|
|
};
|
|
|
|
static const struct of_device_id disp_cc_sdm845_match_table[] = {
|
|
{ .compatible = "qcom,sdm845-dispcc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, disp_cc_sdm845_match_table);
|
|
|
|
static int disp_cc_sdm845_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
struct alpha_pll_config disp_cc_pll0_config = {};
|
|
|
|
regmap = qcom_cc_map(pdev, &disp_cc_sdm845_desc);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
disp_cc_pll0_config.l = 0x2c;
|
|
disp_cc_pll0_config.alpha = 0xcaaa;
|
|
|
|
clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
|
|
|
/* Enable hardware clock gating for DSI and MDP clocks */
|
|
regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0);
|
|
|
|
return qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap);
|
|
}
|
|
|
|
static struct platform_driver disp_cc_sdm845_driver = {
|
|
.probe = disp_cc_sdm845_probe,
|
|
.driver = {
|
|
.name = "disp_cc-sdm845",
|
|
.of_match_table = disp_cc_sdm845_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init disp_cc_sdm845_init(void)
|
|
{
|
|
return platform_driver_register(&disp_cc_sdm845_driver);
|
|
}
|
|
subsys_initcall(disp_cc_sdm845_init);
|
|
|
|
static void __exit disp_cc_sdm845_exit(void)
|
|
{
|
|
platform_driver_unregister(&disp_cc_sdm845_driver);
|
|
}
|
|
module_exit(disp_cc_sdm845_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("QTI DISPCC SDM845 Driver");
|