Dan Williams 172738bbcc cxl/port: Link the 'parent_dport' in portX/ and endpointX/ sysfs ... Similar to the justification in: 1b58b4cac6 ("cxl/port: Record parent dport when adding ports") ...userspace wants to know the routing information for ports for calculating the memdev order for region creation among other things. Cache the information the kernel discovers at enumeration time in a 'parent_dport' attribute to save userspace the time of trawling sysfs to recover the same information. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/167124082375.1626103.6047000000121298560.stgit@dwillia2-xfh.jf.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2023-01-25 15:32:57 -08:00
..
core	cxl/port: Link the 'parent_dport' in portX/ and endpointX/ sysfs	2023-01-25 15:32:57 -08:00
Kconfig	cxl/region: Manage CPU caches relative to DPA invalidation events	2022-12-03 00:03:57 -08:00
Makefile	cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation	2022-11-30 16:30:47 -08:00
acpi.c	cxl: update names for interleave ways conversion macros	2022-12-05 18:17:16 -08:00
cxl.h	cxl/pci: Move tracepoint definitions to drivers/cxl/core/	2023-01-04 17:11:11 -08:00
cxlmem.h	cxl/mbox: Add variable output size validation for internal commands	2022-12-06 14:36:02 -08:00
cxlpci.h	cxl/pci: Move tracepoint definitions to drivers/cxl/core/	2023-01-04 17:11:11 -08:00
mem.c	cxl/port: Add RCD endpoint port enumeration	2022-12-05 10:32:26 -08:00
pci.c	cxl/pci: Show opcode in debug messages when sending a command	2023-01-24 17:52:54 -08:00
pmem.c	cxl/mbox: Enable cxl_mbox_send_cmd() users to validate output size	2022-12-06 14:36:02 -08:00
port.c	cxl/port: Read CDAT table	2022-07-19 15:38:05 -07:00
security.c	cxl/mbox: Enable cxl_mbox_send_cmd() users to validate output size	2022-12-06 14:36:02 -08:00