403 lines
10 KiB
C
403 lines
10 KiB
C
/*
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* linux/arch/arm/mach-pxa/pxa25x.c
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* Code specific to PXA21x/25x/26x variants.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Since this file should be linked before any other machine specific file,
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* the __initcall() here will be executed first. This serves as default
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* initialization stuff for PXA machines which can be overridden later if
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* need be.
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*/
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#include <linux/gpio.h>
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#include <linux/gpio-pxa.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/suspend.h>
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#include <linux/syscore_ops.h>
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#include <linux/irq.h>
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#include <asm/mach/map.h>
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#include <asm/suspend.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <mach/pxa25x.h>
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#include <mach/reset.h>
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#include <mach/pm.h>
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#include <mach/dma.h>
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#include <mach/smemc.h>
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#include "generic.h"
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#include "devices.h"
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#include "clock.h"
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/*
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* Various clock factors driven by the CCCR register.
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*/
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/* Crystal Frequency to Memory Frequency Multiplier (L) */
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static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
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/* Memory Frequency to Run Mode Frequency Multiplier (M) */
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static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
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/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
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/* Note: we store the value N * 2 here. */
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static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
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/* Crystal clock */
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#define BASE_CLK 3686400
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/*
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* Get the clock frequency as reflected by CCCR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa25x_get_clk_frequency_khz(int info)
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{
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unsigned long cccr, turbo;
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unsigned int l, L, m, M, n2, N;
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cccr = CCCR;
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asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
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l = L_clk_mult[(cccr >> 0) & 0x1f];
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m = M_clk_mult[(cccr >> 5) & 0x03];
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n2 = N2_clk_mult[(cccr >> 7) & 0x07];
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L = l * BASE_CLK;
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M = m * L;
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N = n2 * M / 2;
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if(info)
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{
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L += 5000;
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printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
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L / 1000000, (L % 1000000) / 10000, l );
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M += 5000;
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printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
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M / 1000000, (M % 1000000) / 10000, m );
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N += 5000;
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printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
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N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
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(turbo & 1) ? "" : "in" );
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}
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return (turbo & 1) ? (N/1000) : (M/1000);
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}
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static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
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{
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return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
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}
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static const struct clkops clk_pxa25x_mem_ops = {
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.enable = clk_dummy_enable,
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.disable = clk_dummy_disable,
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.getrate = clk_pxa25x_mem_getrate,
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};
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static const struct clkops clk_pxa25x_lcd_ops = {
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.enable = clk_pxa2xx_cken_enable,
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.disable = clk_pxa2xx_cken_disable,
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.getrate = clk_pxa25x_mem_getrate,
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};
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static unsigned long gpio12_config_32k[] = {
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GPIO12_32KHz,
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};
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static unsigned long gpio12_config_gpio[] = {
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GPIO12_GPIO,
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};
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static void clk_gpio12_enable(struct clk *clk)
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{
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pxa2xx_mfp_config(gpio12_config_32k, 1);
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}
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static void clk_gpio12_disable(struct clk *clk)
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{
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pxa2xx_mfp_config(gpio12_config_gpio, 1);
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}
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static const struct clkops clk_pxa25x_gpio12_ops = {
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.enable = clk_gpio12_enable,
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.disable = clk_gpio12_disable,
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};
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static unsigned long gpio11_config_3m6[] = {
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GPIO11_3_6MHz,
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};
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static unsigned long gpio11_config_gpio[] = {
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GPIO11_GPIO,
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};
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static void clk_gpio11_enable(struct clk *clk)
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{
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pxa2xx_mfp_config(gpio11_config_3m6, 1);
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}
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static void clk_gpio11_disable(struct clk *clk)
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{
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pxa2xx_mfp_config(gpio11_config_gpio, 1);
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}
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static const struct clkops clk_pxa25x_gpio11_ops = {
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.enable = clk_gpio11_enable,
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.disable = clk_gpio11_disable,
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};
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/*
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* 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
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* 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
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* 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
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*/
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/*
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* PXA 2xx clock declarations.
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*/
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static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
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static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
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static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
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static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
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static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
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static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
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static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
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static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
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static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
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static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
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static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
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static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
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static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
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static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
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static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);
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static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
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static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
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static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
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static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
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static struct clk_lookup pxa25x_clkregs[] = {
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INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
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INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
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INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
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INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
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INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
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INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
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INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
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INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
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INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
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INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
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INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
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INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
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INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
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INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
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INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
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INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
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INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
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INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
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INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
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#ifdef CONFIG_CPU_PXA26x
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INIT_CLKREG(&clk_dummy, "pxa26x-gpio", NULL),
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#else
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INIT_CLKREG(&clk_dummy, "pxa25x-gpio", NULL),
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#endif
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INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
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};
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static struct clk_lookup pxa25x_hwuart_clkreg =
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INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
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#ifdef CONFIG_PM
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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/*
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* List of global PXA peripheral registers to preserve.
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* More ones like CP and general purpose register values are preserved
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* with the stack pointer in sleep.S.
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*/
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enum {
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SLEEP_SAVE_PSTR,
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SLEEP_SAVE_COUNT
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};
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static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
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{
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SAVE(PSTR);
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}
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static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
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{
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RESTORE(PSTR);
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}
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static void pxa25x_cpu_pm_enter(suspend_state_t state)
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{
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/* Clear reset status */
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RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
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switch (state) {
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case PM_SUSPEND_MEM:
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cpu_suspend(PWRMODE_SLEEP, pxa25x_finish_suspend);
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break;
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}
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}
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static int pxa25x_cpu_pm_prepare(void)
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{
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/* set resume return address */
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PSPR = virt_to_phys(cpu_resume);
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return 0;
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}
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static void pxa25x_cpu_pm_finish(void)
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{
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/* ensure not to come back here if it wasn't intended */
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PSPR = 0;
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}
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static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
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.save_count = SLEEP_SAVE_COUNT,
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.valid = suspend_valid_only_mem,
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.save = pxa25x_cpu_pm_save,
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.restore = pxa25x_cpu_pm_restore,
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.enter = pxa25x_cpu_pm_enter,
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.prepare = pxa25x_cpu_pm_prepare,
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.finish = pxa25x_cpu_pm_finish,
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};
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static void __init pxa25x_init_pm(void)
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{
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pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
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}
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#else
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static inline void pxa25x_init_pm(void) {}
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#endif
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/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
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*/
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static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
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{
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int gpio = pxa_irq_to_gpio(d->irq);
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uint32_t mask = 0;
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if (gpio >= 0 && gpio < 85)
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return gpio_set_wake(gpio, on);
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if (d->irq == IRQ_RTCAlrm) {
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mask = PWER_RTC;
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goto set_pwer;
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}
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return -EINVAL;
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set_pwer:
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if (on)
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PWER |= mask;
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else
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PWER &=~mask;
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return 0;
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}
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void __init pxa25x_init_irq(void)
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{
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pxa_init_irq(32, pxa25x_set_wake);
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}
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#ifdef CONFIG_CPU_PXA26x
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void __init pxa26x_init_irq(void)
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{
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pxa_init_irq(32, pxa25x_set_wake);
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}
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#endif
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static struct map_desc pxa25x_io_desc[] __initdata = {
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{ /* Mem Ctl */
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.virtual = (unsigned long)SMEMC_VIRT,
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.pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
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.length = SMEMC_SIZE,
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.type = MT_DEVICE
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}, { /* UNCACHED_PHYS_0 */
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.virtual = UNCACHED_PHYS_0,
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.pfn = __phys_to_pfn(0x00000000),
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.length = UNCACHED_PHYS_0_SIZE,
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.type = MT_DEVICE
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},
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};
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void __init pxa25x_map_io(void)
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{
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pxa_map_io();
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iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
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pxa25x_get_clk_frequency_khz(1);
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}
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static struct pxa_gpio_platform_data pxa25x_gpio_info __initdata = {
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.irq_base = PXA_GPIO_TO_IRQ(0),
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.gpio_set_wake = gpio_set_wake,
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};
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static struct platform_device *pxa25x_devices[] __initdata = {
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&pxa25x_device_udc,
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&pxa_device_pmu,
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&pxa_device_i2s,
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&sa1100_device_rtc,
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&pxa25x_device_ssp,
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&pxa25x_device_nssp,
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&pxa25x_device_assp,
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&pxa25x_device_pwm0,
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&pxa25x_device_pwm1,
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&pxa_device_asoc_platform,
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};
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static int __init pxa25x_init(void)
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{
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int ret = 0;
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if (cpu_is_pxa25x()) {
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reset_status = RCSR;
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clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
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if ((ret = pxa_init_dma(IRQ_DMA, 16)))
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return ret;
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pxa25x_init_pm();
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register_syscore_ops(&pxa_irq_syscore_ops);
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register_syscore_ops(&pxa2xx_mfp_syscore_ops);
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register_syscore_ops(&pxa2xx_clock_syscore_ops);
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pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info);
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ret = platform_add_devices(pxa25x_devices,
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ARRAY_SIZE(pxa25x_devices));
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if (ret)
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return ret;
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}
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/* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
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if (cpu_is_pxa255())
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clkdev_add(&pxa25x_hwuart_clkreg);
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return ret;
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}
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postcore_initcall(pxa25x_init);
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