Conor Dooley d39fb17276 clk: microchip: add PolarFire SoC fabric clock support ... Add a driver to support the PLLs in PolarFire SoC's Clock Conditioning Circuitry, an instance of which is located in each ordinal corner of the FPGA. Only get_rate() is supported as these clocks are intended to be statically configured by the FPGA design. Currently, the DLLs are not supported by this driver. For more information on the hardware, see "PolarFire SoC FPGA Clocking Resources" in the link below. Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220908143651.1252601-5-conor.dooley@microchip.com		2022-09-14 10:57:07 +03:00
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Kconfig	clk: microchip: mpfs: add reset controller	2022-09-14 10:55:17 +03:00
Makefile	clk: microchip: add PolarFire SoC fabric clock support	2022-09-14 10:57:07 +03:00
clk-core.c	clk: let init callback return an error code	2019-12-23 18:53:13 -08:00
clk-core.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 445	2019-06-05 17:37:18 +02:00
clk-mpfs-ccc.c	clk: microchip: add PolarFire SoC fabric clock support	2022-09-14 10:57:07 +03:00
clk-mpfs.c	clk: microchip: mpfs: update module authorship & licencing	2022-09-14 10:57:07 +03:00
clk-pic32mzda.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 445	2019-06-05 17:37:18 +02:00