1111 lines
28 KiB
C
1111 lines
28 KiB
C
/*
|
|
*
|
|
* Copyright (C) 2013 Texas Instruments Incorporated
|
|
*
|
|
* Hwmod common for AM335x and AM43x
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation version 2.
|
|
*
|
|
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
|
* kind, whether express or implied; without even the implied warranty
|
|
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#include <linux/types.h>
|
|
|
|
#include "omap_hwmod.h"
|
|
#include "wd_timer.h"
|
|
#include "cm33xx.h"
|
|
#include "prm33xx.h"
|
|
#include "omap_hwmod_33xx_43xx_common_data.h"
|
|
#include "prcm43xx.h"
|
|
#include "common.h"
|
|
|
|
#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
|
|
#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
|
|
#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
|
|
#define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
|
|
|
|
/*
|
|
* 'l3' class
|
|
* instance(s): l3_main, l3_s, l3_instr
|
|
*/
|
|
static struct omap_hwmod_class am33xx_l3_hwmod_class = {
|
|
.name = "l3",
|
|
};
|
|
|
|
struct omap_hwmod am33xx_l3_main_hwmod = {
|
|
.name = "l3_main",
|
|
.class = &am33xx_l3_hwmod_class,
|
|
.clkdm_name = "l3_clkdm",
|
|
.flags = HWMOD_INIT_NO_IDLE,
|
|
.main_clk = "l3_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* l3_s */
|
|
struct omap_hwmod am33xx_l3_s_hwmod = {
|
|
.name = "l3_s",
|
|
.class = &am33xx_l3_hwmod_class,
|
|
.clkdm_name = "l3s_clkdm",
|
|
};
|
|
|
|
/* l3_instr */
|
|
struct omap_hwmod am33xx_l3_instr_hwmod = {
|
|
.name = "l3_instr",
|
|
.class = &am33xx_l3_hwmod_class,
|
|
.clkdm_name = "l3_clkdm",
|
|
.flags = HWMOD_INIT_NO_IDLE,
|
|
.main_clk = "l3_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'l4' class
|
|
* instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
|
|
*/
|
|
struct omap_hwmod_class am33xx_l4_hwmod_class = {
|
|
.name = "l4",
|
|
};
|
|
|
|
/* l4_ls */
|
|
struct omap_hwmod am33xx_l4_ls_hwmod = {
|
|
.name = "l4_ls",
|
|
.class = &am33xx_l4_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_INIT_NO_IDLE,
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* l4_wkup */
|
|
struct omap_hwmod am33xx_l4_wkup_hwmod = {
|
|
.name = "l4_wkup",
|
|
.class = &am33xx_l4_hwmod_class,
|
|
.clkdm_name = "l4_wkup_clkdm",
|
|
.flags = HWMOD_INIT_NO_IDLE,
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'mpu' class
|
|
*/
|
|
static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
|
|
.name = "mpu",
|
|
};
|
|
|
|
struct omap_hwmod am33xx_mpu_hwmod = {
|
|
.name = "mpu",
|
|
.class = &am33xx_mpu_hwmod_class,
|
|
.clkdm_name = "mpu_clkdm",
|
|
.flags = HWMOD_INIT_NO_IDLE,
|
|
.main_clk = "dpll_mpu_m2_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'wakeup m3' class
|
|
* Wakeup controller sub-system under wakeup domain
|
|
*/
|
|
struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
|
|
.name = "wkup_m3",
|
|
};
|
|
|
|
/*
|
|
* 'pru-icss' class
|
|
* Programmable Real-Time Unit and Industrial Communication Subsystem
|
|
*/
|
|
static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
|
|
.name = "pruss",
|
|
};
|
|
|
|
static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
|
|
{ .name = "pruss", .rst_shift = 1 },
|
|
};
|
|
|
|
/* pru-icss */
|
|
/* Pseudo hwmod for reset control purpose only */
|
|
struct omap_hwmod am33xx_pruss_hwmod = {
|
|
.name = "pruss",
|
|
.class = &am33xx_pruss_hwmod_class,
|
|
.clkdm_name = "pruss_ocp_clkdm",
|
|
.main_clk = "pruss_ocp_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.rst_lines = am33xx_pruss_resets,
|
|
.rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
|
|
};
|
|
|
|
/* gfx */
|
|
/* Pseudo hwmod for reset control purpose only */
|
|
static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
|
|
.name = "gfx",
|
|
};
|
|
|
|
static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
|
|
{ .name = "gfx", .rst_shift = 0, .st_shift = 0},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_gfx_hwmod = {
|
|
.name = "gfx",
|
|
.class = &am33xx_gfx_hwmod_class,
|
|
.clkdm_name = "gfx_l3_clkdm",
|
|
.main_clk = "gfx_fck_div_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.rst_lines = am33xx_gfx_resets,
|
|
.rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
|
|
};
|
|
|
|
/*
|
|
* 'prcm' class
|
|
* power and reset manager (whole prcm infrastructure)
|
|
*/
|
|
static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
|
|
.name = "prcm",
|
|
};
|
|
|
|
/* prcm */
|
|
struct omap_hwmod am33xx_prcm_hwmod = {
|
|
.name = "prcm",
|
|
.class = &am33xx_prcm_hwmod_class,
|
|
.clkdm_name = "l4_wkup_clkdm",
|
|
};
|
|
|
|
/*
|
|
* 'emif' class
|
|
* instance(s): emif
|
|
*/
|
|
static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
|
|
.rev_offs = 0x0000,
|
|
};
|
|
|
|
struct omap_hwmod_class am33xx_emif_hwmod_class = {
|
|
.name = "emif",
|
|
.sysc = &am33xx_emif_sysc,
|
|
};
|
|
|
|
/*
|
|
* 'aes0' class
|
|
*/
|
|
static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
|
|
.rev_offs = 0x80,
|
|
.sysc_offs = 0x84,
|
|
.syss_offs = 0x88,
|
|
.sysc_flags = SYSS_HAS_RESET_STATUS,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
|
|
.name = "aes0",
|
|
.sysc = &am33xx_aes0_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_aes0_hwmod = {
|
|
.name = "aes",
|
|
.class = &am33xx_aes0_hwmod_class,
|
|
.clkdm_name = "l3_clkdm",
|
|
.main_clk = "aes0_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* sha0 HIB2 (the 'P' (public) device) */
|
|
static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
|
|
.rev_offs = 0x100,
|
|
.sysc_offs = 0x110,
|
|
.syss_offs = 0x114,
|
|
.sysc_flags = SYSS_HAS_RESET_STATUS,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
|
|
.name = "sha0",
|
|
.sysc = &am33xx_sha0_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_sha0_hwmod = {
|
|
.name = "sham",
|
|
.class = &am33xx_sha0_hwmod_class,
|
|
.clkdm_name = "l3_clkdm",
|
|
.main_clk = "l3_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* rng */
|
|
static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
|
|
.rev_offs = 0x1fe0,
|
|
.sysc_offs = 0x1fe4,
|
|
.sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
|
|
.idlemodes = SIDLE_FORCE | SIDLE_NO,
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_rng_hwmod_class = {
|
|
.name = "rng",
|
|
.sysc = &am33xx_rng_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_rng_hwmod = {
|
|
.name = "rng",
|
|
.class = &am33xx_rng_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_SWSUP_SIDLE,
|
|
.main_clk = "rng_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* ocmcram */
|
|
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
|
|
.name = "ocmcram",
|
|
};
|
|
|
|
struct omap_hwmod am33xx_ocmcram_hwmod = {
|
|
.name = "ocmcram",
|
|
.class = &am33xx_ocmcram_hwmod_class,
|
|
.clkdm_name = "l3_clkdm",
|
|
.flags = HWMOD_INIT_NO_IDLE,
|
|
.main_clk = "l3_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* 'smartreflex' class */
|
|
static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
|
|
.name = "smartreflex",
|
|
};
|
|
|
|
/* smartreflex0 */
|
|
struct omap_hwmod am33xx_smartreflex0_hwmod = {
|
|
.name = "smartreflex0",
|
|
.class = &am33xx_smartreflex_hwmod_class,
|
|
.clkdm_name = "l4_wkup_clkdm",
|
|
.main_clk = "smartreflex0_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* smartreflex1 */
|
|
struct omap_hwmod am33xx_smartreflex1_hwmod = {
|
|
.name = "smartreflex1",
|
|
.class = &am33xx_smartreflex_hwmod_class,
|
|
.clkdm_name = "l4_wkup_clkdm",
|
|
.main_clk = "smartreflex1_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'control' module class
|
|
*/
|
|
struct omap_hwmod_class am33xx_control_hwmod_class = {
|
|
.name = "control",
|
|
};
|
|
|
|
/*
|
|
* dcan class
|
|
*/
|
|
static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
|
|
.name = "d_can",
|
|
};
|
|
|
|
/* dcan0 */
|
|
struct omap_hwmod am33xx_dcan0_hwmod = {
|
|
.name = "d_can0",
|
|
.class = &am33xx_dcan_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "dcan0_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* dcan1 */
|
|
struct omap_hwmod am33xx_dcan1_hwmod = {
|
|
.name = "d_can1",
|
|
.class = &am33xx_dcan_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "dcan1_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* elm */
|
|
static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
|
|
SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_elm_hwmod_class = {
|
|
.name = "elm",
|
|
.sysc = &am33xx_elm_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_elm_hwmod = {
|
|
.name = "elm",
|
|
.class = &am33xx_elm_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* pwmss */
|
|
static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
|
|
.rev_offs = 0x0,
|
|
.sysc_offs = 0x4,
|
|
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
|
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
|
|
.name = "epwmss",
|
|
.sysc = &am33xx_epwmss_sysc,
|
|
};
|
|
|
|
/* epwmss0 */
|
|
struct omap_hwmod am33xx_epwmss0_hwmod = {
|
|
.name = "epwmss0",
|
|
.class = &am33xx_epwmss_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* epwmss1 */
|
|
struct omap_hwmod am33xx_epwmss1_hwmod = {
|
|
.name = "epwmss1",
|
|
.class = &am33xx_epwmss_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* epwmss2 */
|
|
struct omap_hwmod am33xx_epwmss2_hwmod = {
|
|
.name = "epwmss2",
|
|
.class = &am33xx_epwmss_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'gpio' class: for gpio 0,1,2,3
|
|
*/
|
|
static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0114,
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
|
|
.name = "gpio",
|
|
.sysc = &am33xx_gpio_sysc,
|
|
};
|
|
|
|
/* gpio1 */
|
|
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
|
|
{ .role = "dbclk", .clk = "gpio1_dbclk" },
|
|
};
|
|
|
|
static struct omap_hwmod am33xx_gpio1_hwmod = {
|
|
.name = "gpio2",
|
|
.class = &am33xx_gpio_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.opt_clks = gpio1_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
|
|
};
|
|
|
|
/* gpio2 */
|
|
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
|
|
{ .role = "dbclk", .clk = "gpio2_dbclk" },
|
|
};
|
|
|
|
static struct omap_hwmod am33xx_gpio2_hwmod = {
|
|
.name = "gpio3",
|
|
.class = &am33xx_gpio_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.opt_clks = gpio2_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
|
|
};
|
|
|
|
/* gpio3 */
|
|
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
|
|
{ .role = "dbclk", .clk = "gpio3_dbclk" },
|
|
};
|
|
|
|
static struct omap_hwmod am33xx_gpio3_hwmod = {
|
|
.name = "gpio4",
|
|
.class = &am33xx_gpio_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.opt_clks = gpio3_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
|
|
};
|
|
|
|
/* gpmc */
|
|
static struct omap_hwmod_class_sysconfig gpmc_sysc = {
|
|
.rev_offs = 0x0,
|
|
.sysc_offs = 0x10,
|
|
.syss_offs = 0x14,
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
|
|
.name = "gpmc",
|
|
.sysc = &gpmc_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_gpmc_hwmod = {
|
|
.name = "gpmc",
|
|
.class = &am33xx_gpmc_hwmod_class,
|
|
.clkdm_name = "l3s_clkdm",
|
|
/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
|
|
.flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
|
|
.main_clk = "l3s_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'mailbox' class
|
|
* mailbox module allowing communication between the on-chip processors using a
|
|
* queued mailbox-interrupt mechanism.
|
|
*/
|
|
static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
|
|
.name = "mailbox",
|
|
.sysc = &am33xx_mailbox_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_mailbox_hwmod = {
|
|
.name = "mailbox",
|
|
.class = &am33xx_mailbox_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'mcasp' class
|
|
*/
|
|
static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
|
|
.rev_offs = 0x0,
|
|
.sysc_offs = 0x4,
|
|
.sysc_flags = SYSC_HAS_SIDLEMODE,
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type3,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
|
|
.name = "mcasp",
|
|
.sysc = &am33xx_mcasp_sysc,
|
|
};
|
|
|
|
/* mcasp0 */
|
|
struct omap_hwmod am33xx_mcasp0_hwmod = {
|
|
.name = "mcasp0",
|
|
.class = &am33xx_mcasp_hwmod_class,
|
|
.clkdm_name = "l3s_clkdm",
|
|
.main_clk = "mcasp0_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* mcasp1 */
|
|
struct omap_hwmod am33xx_mcasp1_hwmod = {
|
|
.name = "mcasp1",
|
|
.class = &am33xx_mcasp_hwmod_class,
|
|
.clkdm_name = "l3s_clkdm",
|
|
.main_clk = "mcasp1_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'rtc' class
|
|
* rtc subsystem
|
|
*/
|
|
static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
|
|
.rev_offs = 0x0074,
|
|
.sysc_offs = 0x0078,
|
|
.sysc_flags = SYSC_HAS_SIDLEMODE,
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO |
|
|
SIDLE_SMART | SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type3,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
|
|
.name = "rtc",
|
|
.sysc = &am33xx_rtc_sysc,
|
|
.unlock = &omap_hwmod_rtc_unlock,
|
|
.lock = &omap_hwmod_rtc_lock,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_rtc_hwmod = {
|
|
.name = "rtc",
|
|
.class = &am33xx_rtc_hwmod_class,
|
|
.clkdm_name = "l4_rtc_clkdm",
|
|
.main_clk = "clk_32768_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* 'spi' class */
|
|
static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0110,
|
|
.syss_offs = 0x0114,
|
|
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
|
|
SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
struct omap_hwmod_class am33xx_spi_hwmod_class = {
|
|
.name = "mcspi",
|
|
.sysc = &am33xx_mcspi_sysc,
|
|
};
|
|
|
|
/* spi0 */
|
|
struct omap_hwmod am33xx_spi0_hwmod = {
|
|
.name = "spi0",
|
|
.class = &am33xx_spi_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "dpll_per_m2_div4_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* spi1 */
|
|
struct omap_hwmod am33xx_spi1_hwmod = {
|
|
.name = "spi1",
|
|
.class = &am33xx_spi_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "dpll_per_m2_div4_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'spinlock' class
|
|
* spinlock provides hardware assistance for synchronizing the
|
|
* processes running on multiple processors
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
|
|
.name = "spinlock",
|
|
.sysc = &am33xx_spinlock_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_spinlock_hwmod = {
|
|
.name = "spinlock",
|
|
.class = &am33xx_spinlock_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* 'timer 2-7' class */
|
|
static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
SYSC_HAS_RESET_STATUS,
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
struct omap_hwmod_class am33xx_timer_hwmod_class = {
|
|
.name = "timer",
|
|
.sysc = &am33xx_timer_sysc,
|
|
};
|
|
|
|
/* timer1 1ms */
|
|
static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
|
|
SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
|
|
.name = "timer",
|
|
.sysc = &am33xx_timer1ms_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer1_hwmod = {
|
|
.name = "timer1",
|
|
.class = &am33xx_timer1ms_hwmod_class,
|
|
.clkdm_name = "l4_wkup_clkdm",
|
|
.main_clk = "timer1_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer2_hwmod = {
|
|
.name = "timer2",
|
|
.class = &am33xx_timer_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "timer2_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer3_hwmod = {
|
|
.name = "timer3",
|
|
.class = &am33xx_timer_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "timer3_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer4_hwmod = {
|
|
.name = "timer4",
|
|
.class = &am33xx_timer_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "timer4_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer5_hwmod = {
|
|
.name = "timer5",
|
|
.class = &am33xx_timer_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "timer5_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer6_hwmod = {
|
|
.name = "timer6",
|
|
.class = &am33xx_timer_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "timer6_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer7_hwmod = {
|
|
.name = "timer7",
|
|
.class = &am33xx_timer_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "timer7_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* tpcc */
|
|
static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
|
|
.name = "tpcc",
|
|
};
|
|
|
|
struct omap_hwmod am33xx_tpcc_hwmod = {
|
|
.name = "tpcc",
|
|
.class = &am33xx_tpcc_hwmod_class,
|
|
.clkdm_name = "l3_clkdm",
|
|
.main_clk = "l3_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
|
|
.rev_offs = 0x0,
|
|
.sysc_offs = 0x10,
|
|
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
SYSC_HAS_MIDLEMODE),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
/* 'tptc' class */
|
|
static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
|
|
.name = "tptc",
|
|
.sysc = &am33xx_tptc_sysc,
|
|
};
|
|
|
|
/* tptc0 */
|
|
struct omap_hwmod am33xx_tptc0_hwmod = {
|
|
.name = "tptc0",
|
|
.class = &am33xx_tptc_hwmod_class,
|
|
.clkdm_name = "l3_clkdm",
|
|
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
|
.main_clk = "l3_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* tptc1 */
|
|
struct omap_hwmod am33xx_tptc1_hwmod = {
|
|
.name = "tptc1",
|
|
.class = &am33xx_tptc_hwmod_class,
|
|
.clkdm_name = "l3_clkdm",
|
|
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
|
|
.main_clk = "l3_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* tptc2 */
|
|
struct omap_hwmod am33xx_tptc2_hwmod = {
|
|
.name = "tptc2",
|
|
.class = &am33xx_tptc_hwmod_class,
|
|
.clkdm_name = "l3_clkdm",
|
|
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
|
|
.main_clk = "l3_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* 'wd_timer' class */
|
|
static struct omap_hwmod_class_sysconfig wdt_sysc = {
|
|
.rev_offs = 0x0,
|
|
.sysc_offs = 0x10,
|
|
.syss_offs = 0x14,
|
|
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
|
|
.name = "wd_timer",
|
|
.sysc = &wdt_sysc,
|
|
.pre_shutdown = &omap2_wd_timer_disable,
|
|
};
|
|
|
|
/*
|
|
* XXX: device.c file uses hardcoded name for watchdog timer
|
|
* driver "wd_timer2, so we are also using same name as of now...
|
|
*/
|
|
struct omap_hwmod am33xx_wd_timer1_hwmod = {
|
|
.name = "wd_timer2",
|
|
.class = &am33xx_wd_timer_hwmod_class,
|
|
.clkdm_name = "l4_wkup_clkdm",
|
|
.flags = HWMOD_SWSUP_SIDLE,
|
|
.main_clk = "wdt1_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
static void omap_hwmod_am33xx_clkctrl(void)
|
|
{
|
|
CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_smartreflex0_hwmod,
|
|
AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_smartreflex1_hwmod,
|
|
AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
|
|
PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
|
|
}
|
|
|
|
static void omap_hwmod_am33xx_rst(void)
|
|
{
|
|
RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
|
|
RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
|
|
RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
|
|
}
|
|
|
|
void omap_hwmod_am33xx_reg(void)
|
|
{
|
|
omap_hwmod_am33xx_clkctrl();
|
|
omap_hwmod_am33xx_rst();
|
|
}
|
|
|
|
static void omap_hwmod_am43xx_clkctrl(void)
|
|
{
|
|
CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_smartreflex0_hwmod,
|
|
AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_smartreflex1_hwmod,
|
|
AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
|
|
}
|
|
|
|
static void omap_hwmod_am43xx_rst(void)
|
|
{
|
|
RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
|
|
RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
|
|
RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
|
|
RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
|
|
}
|
|
|
|
void omap_hwmod_am43xx_reg(void)
|
|
{
|
|
omap_hwmod_am43xx_clkctrl();
|
|
omap_hwmod_am43xx_rst();
|
|
}
|