942 lines
32 KiB
C
942 lines
32 KiB
C
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
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*/
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/*
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _I915_DRV_H_
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#define _I915_DRV_H_
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#include <uapi/drm/i915_drm.h>
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#include <linux/pm_qos.h>
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#include <drm/ttm/ttm_device.h>
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#include "display/intel_display_limits.h"
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#include "display/intel_display_core.h"
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#include "gem/i915_gem_context_types.h"
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#include "gem/i915_gem_shrinker.h"
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#include "gem/i915_gem_stolen.h"
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#include "gt/intel_engine.h"
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#include "gt/intel_gt_types.h"
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#include "gt/intel_region_lmem.h"
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#include "gt/intel_workarounds.h"
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#include "gt/uc/intel_uc.h"
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#include "soc/intel_pch.h"
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#include "i915_drm_client.h"
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#include "i915_gem.h"
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#include "i915_gpu_error.h"
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#include "i915_params.h"
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#include "i915_perf_types.h"
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#include "i915_scheduler.h"
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#include "i915_utils.h"
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#include "intel_device_info.h"
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#include "intel_memory_region.h"
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#include "intel_runtime_pm.h"
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#include "intel_step.h"
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#include "intel_uncore.h"
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struct drm_i915_clock_gating_funcs;
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struct vlv_s0ix_state;
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struct intel_pxp;
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#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
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/* Data Stolen Memory (DSM) aka "i915 stolen memory" */
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struct i915_dsm {
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/*
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* The start and end of DSM which we can optionally use to create GEM
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* objects backed by stolen memory.
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*
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* Note that usable_size tells us exactly how much of this we are
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* actually allowed to use, given that some portion of it is in fact
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* reserved for use by hardware functions.
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*/
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struct resource stolen;
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/*
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* Reserved portion of DSM.
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*/
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struct resource reserved;
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/*
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* Total size minus reserved ranges.
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*
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* DSM is segmented in hardware with different portions offlimits to
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* certain functions.
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*
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* The drm_mm is initialised to the total accessible range, as found
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* from the PCI config. On Broadwell+, this is further restricted to
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* avoid the first page! The upper end of DSM is reserved for hardware
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* functions and similarly removed from the accessible range.
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*/
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resource_size_t usable_size;
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};
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struct i915_suspend_saved_registers {
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u32 saveDSPARB;
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u32 saveSWF0[16];
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u32 saveSWF1[16];
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u32 saveSWF3[3];
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u16 saveGCDGMBUS;
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};
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#define MAX_L3_SLICES 2
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struct intel_l3_parity {
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u32 *remap_info[MAX_L3_SLICES];
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struct work_struct error_work;
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int which_slice;
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};
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struct i915_gem_mm {
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/*
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* Shortcut for the stolen region. This points to either
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* INTEL_REGION_STOLEN_SMEM for integrated platforms, or
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* INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
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* support stolen.
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*/
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struct intel_memory_region *stolen_region;
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/** Memory allocator for GTT stolen memory */
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struct drm_mm stolen;
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/** Protects the usage of the GTT stolen memory allocator. This is
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* always the inner lock when overlapping with struct_mutex. */
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struct mutex stolen_lock;
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/* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
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spinlock_t obj_lock;
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/**
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* List of objects which are purgeable.
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*/
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struct list_head purge_list;
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/**
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* List of objects which have allocated pages and are shrinkable.
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*/
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struct list_head shrink_list;
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/**
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* List of objects which are pending destruction.
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*/
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struct llist_head free_list;
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struct work_struct free_work;
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/**
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* Count of objects pending destructions. Used to skip needlessly
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* waiting on an RCU barrier if no objects are waiting to be freed.
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*/
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atomic_t free_count;
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/**
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* tmpfs instance used for shmem backed objects
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*/
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struct vfsmount *gemfs;
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struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
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struct notifier_block oom_notifier;
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struct notifier_block vmap_notifier;
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struct shrinker shrinker;
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#ifdef CONFIG_MMU_NOTIFIER
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/**
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* notifier_lock for mmu notifiers, memory may not be allocated
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* while holding this lock.
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*/
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rwlock_t notifier_lock;
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#endif
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/* shrinker accounting, also useful for userland debugging */
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u64 shrink_memory;
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u32 shrink_count;
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};
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struct i915_virtual_gpu {
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struct mutex lock; /* serialises sending of g2v_notify command pkts */
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bool active;
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u32 caps;
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u32 *initial_mmio;
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u8 *initial_cfg_space;
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struct list_head entry;
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};
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struct i915_selftest_stash {
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atomic_t counter;
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struct ida mock_region_instances;
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};
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struct drm_i915_private {
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struct drm_device drm;
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struct intel_display display;
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/* FIXME: Device release actions should all be moved to drmm_ */
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bool do_release;
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/* i915 device parameters */
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struct i915_params params;
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const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
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struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
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struct intel_driver_caps caps;
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struct i915_dsm dsm;
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struct intel_uncore uncore;
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struct intel_uncore_mmio_debug mmio_debug;
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struct i915_virtual_gpu vgpu;
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struct intel_gvt *gvt;
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struct {
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struct pci_dev *pdev;
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struct resource mch_res;
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bool mchbar_need_disable;
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} gmch;
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struct rb_root uabi_engines;
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unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
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/* protects the irq masks */
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spinlock_t irq_lock;
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bool display_irqs_enabled;
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/* Sideband mailbox protection */
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struct mutex sb_lock;
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struct pm_qos_request sb_qos;
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/** Cached value of IMR to avoid reads in updating the bitfield */
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union {
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u32 irq_mask;
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u32 de_irq_mask[I915_MAX_PIPES];
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};
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u32 pipestat_irq_mask[I915_MAX_PIPES];
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bool preserve_bios_swizzle;
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unsigned int fsb_freq, mem_freq, is_ddr3;
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unsigned int skl_preferred_vco_freq;
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unsigned int max_dotclk_freq;
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unsigned int hpll_freq;
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unsigned int czclk_freq;
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/**
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* wq - Driver workqueue for GEM.
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*
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* NOTE: Work items scheduled here are not allowed to grab any modeset
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* locks, for otherwise the flushing done in the pageflip code will
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* result in deadlocks.
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*/
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struct workqueue_struct *wq;
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/* pm private clock gating functions */
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const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
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/* PCH chipset type */
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enum intel_pch pch_type;
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unsigned short pch_id;
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unsigned long gem_quirks;
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struct i915_gem_mm mm;
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struct intel_l3_parity l3_parity;
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/*
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* edram size in MB.
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* Cannot be determined by PCIID. You must always read a register.
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*/
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u32 edram_size_mb;
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struct i915_gpu_error gpu_error;
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u32 suspend_count;
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struct i915_suspend_saved_registers regfile;
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struct vlv_s0ix_state *vlv_s0ix_state;
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struct dram_info {
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bool wm_lv_0_adjust_needed;
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u8 num_channels;
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bool symmetric_memory;
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enum intel_dram_type {
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INTEL_DRAM_UNKNOWN,
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INTEL_DRAM_DDR3,
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INTEL_DRAM_DDR4,
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INTEL_DRAM_LPDDR3,
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INTEL_DRAM_LPDDR4,
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INTEL_DRAM_DDR5,
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INTEL_DRAM_LPDDR5,
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} type;
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u8 num_qgv_points;
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u8 num_psf_gv_points;
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} dram_info;
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struct intel_runtime_pm runtime_pm;
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struct i915_perf perf;
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struct i915_hwmon *hwmon;
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/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
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struct intel_gt gt0;
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/*
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* i915->gt[0] == &i915->gt0
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*/
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#define I915_MAX_GT 4
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struct intel_gt *gt[I915_MAX_GT];
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struct kobject *sysfs_gt;
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/* Quick lookup of media GT (current platforms only have one) */
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struct intel_gt *media_gt;
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struct {
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struct i915_gem_contexts {
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spinlock_t lock; /* locks list */
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struct list_head list;
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} contexts;
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/*
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* We replace the local file with a global mappings as the
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* backing storage for the mmap is on the device and not
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* on the struct file, and we do not want to prolong the
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* lifetime of the local fd. To minimise the number of
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* anonymous inodes we create, we use a global singleton to
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* share the global mapping.
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*/
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struct file *mmap_singleton;
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} gem;
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struct intel_pxp *pxp;
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/* For i915gm/i945gm vblank irq workaround */
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u8 vblank_enabled;
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bool irq_enabled;
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struct i915_pmu pmu;
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struct i915_drm_clients clients;
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/* The TTM device structure. */
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struct ttm_device bdev;
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I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
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/*
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* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
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* will be rejected. Instead look for a better place.
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*/
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};
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static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
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{
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return container_of(dev, struct drm_i915_private, drm);
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}
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static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
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{
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return dev_get_drvdata(kdev);
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}
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static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
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{
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return pci_get_drvdata(pdev);
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}
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static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
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{
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return &i915->gt0;
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}
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/* Simple iterator over all initialised engines */
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#define for_each_engine(engine__, dev_priv__, id__) \
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for ((id__) = 0; \
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(id__) < I915_NUM_ENGINES; \
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(id__)++) \
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for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
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/* Iterator over subset of engines selected by mask */
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#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
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for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
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(tmp__) ? \
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((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
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0;)
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#define rb_to_uabi_engine(rb) \
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rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
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#define for_each_uabi_engine(engine__, i915__) \
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for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
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(engine__); \
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(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
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#define for_each_uabi_class_engine(engine__, class__, i915__) \
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for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
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(engine__) && (engine__)->uabi_class == (class__); \
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(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
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#define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
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#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
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#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
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#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
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#define IP_VER(ver, rel) ((ver) << 8 | (rel))
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#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
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#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
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RUNTIME_INFO(i915)->graphics.ip.rel)
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#define IS_GRAPHICS_VER(i915, from, until) \
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(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
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#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
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#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
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RUNTIME_INFO(i915)->media.ip.rel)
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#define IS_MEDIA_VER(i915, from, until) \
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(MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
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#define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.ip.ver)
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#define IS_DISPLAY_VER(i915, from, until) \
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(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
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#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
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#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
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#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
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#define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
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#define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
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#define IS_DISPLAY_STEP(__i915, since, until) \
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(drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
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INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
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#define IS_GRAPHICS_STEP(__i915, since, until) \
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(drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
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INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
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#define IS_MEDIA_STEP(__i915, since, until) \
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(drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
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INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
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#define IS_BASEDIE_STEP(__i915, since, until) \
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(drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
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INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
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static __always_inline unsigned int
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__platform_mask_index(const struct intel_runtime_info *info,
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enum intel_platform p)
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{
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const unsigned int pbits =
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BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
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/* Expand the platform_mask array if this fails. */
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BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
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pbits * ARRAY_SIZE(info->platform_mask));
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return p / pbits;
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}
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static __always_inline unsigned int
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__platform_mask_bit(const struct intel_runtime_info *info,
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enum intel_platform p)
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{
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const unsigned int pbits =
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BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
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return p % pbits + INTEL_SUBPLATFORM_BITS;
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}
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static inline u32
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intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
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{
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const unsigned int pi = __platform_mask_index(info, p);
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return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
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}
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static __always_inline bool
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IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
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{
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const struct intel_runtime_info *info = RUNTIME_INFO(i915);
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const unsigned int pi = __platform_mask_index(info, p);
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const unsigned int pb = __platform_mask_bit(info, p);
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BUILD_BUG_ON(!__builtin_constant_p(p));
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return info->platform_mask[pi] & BIT(pb);
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}
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static __always_inline bool
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IS_SUBPLATFORM(const struct drm_i915_private *i915,
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enum intel_platform p, unsigned int s)
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{
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const struct intel_runtime_info *info = RUNTIME_INFO(i915);
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const unsigned int pi = __platform_mask_index(info, p);
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const unsigned int pb = __platform_mask_bit(info, p);
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const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
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const u32 mask = info->platform_mask[pi];
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BUILD_BUG_ON(!__builtin_constant_p(p));
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BUILD_BUG_ON(!__builtin_constant_p(s));
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BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
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/* Shift and test on the MSB position so sign flag can be used. */
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return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
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}
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#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
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#define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
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#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
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#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
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#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
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#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
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#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
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#define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
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#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
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#define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
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#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
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#define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
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#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
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#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
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#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
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#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
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#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
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#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
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#define IS_IRONLAKE_M(dev_priv) \
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(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
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#define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
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#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
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#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 1)
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#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
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#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
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#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
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#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
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#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
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#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
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#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
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#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
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#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
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#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
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#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
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#define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
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IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
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#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
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#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
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#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
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#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
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#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
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#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
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#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)
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#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
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#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
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#define IS_METEORLAKE_M(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
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#define IS_METEORLAKE_P(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
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#define IS_DG2_G10(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
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#define IS_DG2_G11(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
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#define IS_DG2_G12(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
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#define IS_ADLS_RPLS(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
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#define IS_ADLP_N(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
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#define IS_ADLP_RPLP(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
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#define IS_ADLP_RPLU(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
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#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
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(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
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#define IS_BDW_ULT(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
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#define IS_BDW_ULX(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
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#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 3)
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#define IS_HSW_ULT(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
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#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 3)
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#define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 1)
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/* ULX machines are also considered ULT. */
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#define IS_HSW_ULX(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
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#define IS_SKL_ULT(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
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#define IS_SKL_ULX(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
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#define IS_KBL_ULT(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
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#define IS_KBL_ULX(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
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#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 2)
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#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 3)
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#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 4)
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#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 2)
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#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 3)
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#define IS_CFL_ULT(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
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#define IS_CFL_ULX(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
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#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 2)
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#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 3)
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#define IS_CML_ULT(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
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#define IS_CML_ULX(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
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#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 2)
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#define IS_ICL_WITH_PORT_F(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
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#define IS_TGL_UY(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
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#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
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#define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
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(IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
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#define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
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(IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
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#define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
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(IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
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#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
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(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
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#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
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(IS_TIGERLAKE(__i915) && \
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IS_DISPLAY_STEP(__i915, since, until))
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#define IS_RKL_DISPLAY_STEP(p, since, until) \
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(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
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#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
|
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(IS_ALDERLAKE_S(__i915) && \
|
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IS_DISPLAY_STEP(__i915, since, until))
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|
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#define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
|
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(IS_ALDERLAKE_S(__i915) && \
|
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IS_GRAPHICS_STEP(__i915, since, until))
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|
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#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
|
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(IS_ALDERLAKE_P(__i915) && \
|
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IS_DISPLAY_STEP(__i915, since, until))
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|
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#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
|
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(IS_ALDERLAKE_P(__i915) && \
|
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IS_GRAPHICS_STEP(__i915, since, until))
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|
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#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
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(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
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#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
|
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(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
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IS_GRAPHICS_STEP(__i915, since, until))
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#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
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(IS_METEORLAKE(__i915) && \
|
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IS_DISPLAY_STEP(__i915, since, until))
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|
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#define IS_MTL_MEDIA_STEP(__i915, since, until) \
|
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(IS_METEORLAKE(__i915) && \
|
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IS_MEDIA_STEP(__i915, since, until))
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|
|
/*
|
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* DG2 hardware steppings are a bit unusual. The hardware design was forked to
|
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* create three variants (G10, G11, and G12) which each have distinct
|
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* workaround sets. The G11 and G12 forks of the DG2 design reset the GT
|
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* stepping back to "A0" for their first iterations, even though they're more
|
|
* similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
|
|
* functionality and workarounds. However the display stepping does not reset
|
|
* in the same manner --- a specific stepping like "B0" has a consistent
|
|
* meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
|
|
*
|
|
* TLDR: All GT workarounds and stepping-specific logic must be applied in
|
|
* relation to a specific subplatform (G10/G11/G12), whereas display workarounds
|
|
* and stepping-specific logic will be applied with a general DG2-wide stepping
|
|
* number.
|
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*/
|
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#define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
|
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(IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
|
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IS_GRAPHICS_STEP(__i915, since, until))
|
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|
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#define IS_DG2_DISPLAY_STEP(__i915, since, until) \
|
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(IS_DG2(__i915) && \
|
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IS_DISPLAY_STEP(__i915, since, until))
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|
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#define IS_PVC_BD_STEP(__i915, since, until) \
|
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(IS_PONTEVECCHIO(__i915) && \
|
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IS_BASEDIE_STEP(__i915, since, until))
|
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|
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#define IS_PVC_CT_STEP(__i915, since, until) \
|
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(IS_PONTEVECCHIO(__i915) && \
|
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IS_GRAPHICS_STEP(__i915, since, until))
|
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|
|
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
|
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#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
|
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#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
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|
|
#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
|
|
#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
|
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|
|
#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
|
|
unsigned int first__ = (first); \
|
|
unsigned int count__ = (count); \
|
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((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
|
|
})
|
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|
|
#define ENGINE_INSTANCES_MASK(gt, first, count) \
|
|
__ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
|
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|
|
#define RCS_MASK(gt) \
|
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ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
|
|
#define BCS_MASK(gt) \
|
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ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
|
|
#define VDBOX_MASK(gt) \
|
|
ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
|
|
#define VEBOX_MASK(gt) \
|
|
ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
|
|
#define CCS_MASK(gt) \
|
|
ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
|
|
|
|
#define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
|
|
|
|
/*
|
|
* The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
|
|
* All later gens can run the final buffer from the ppgtt
|
|
*/
|
|
#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
|
|
|
|
#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
|
|
#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
|
|
#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
|
|
#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
|
|
#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
|
|
#define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
|
|
|
|
#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
|
|
|
|
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
|
|
(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
|
|
#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
|
|
(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
|
|
|
|
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
|
|
|
|
#define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
|
|
#define HAS_PPGTT(dev_priv) \
|
|
(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
|
|
#define HAS_FULL_PPGTT(dev_priv) \
|
|
(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
|
|
|
|
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
|
|
GEM_BUG_ON((sizes) == 0); \
|
|
((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
|
|
})
|
|
|
|
#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
|
|
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
|
|
(INTEL_INFO(dev_priv)->display.overlay_needs_physical)
|
|
|
|
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
|
|
#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
|
|
|
|
#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
|
|
(IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
|
|
|
|
/* WaRsDisableCoarsePowerGating:skl,cnl */
|
|
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
|
|
(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
|
|
|
|
#define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
|
|
#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
|
|
IS_GEMINILAKE(dev_priv) || \
|
|
IS_KABYLAKE(dev_priv))
|
|
|
|
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
|
|
* rows, which changed the alignment requirements and fence programming.
|
|
*/
|
|
#define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
|
|
!(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
|
|
#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
|
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#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
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#define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
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#define HAS_FBC(dev_priv) (RUNTIME_INFO(dev_priv)->fbc_mask != 0)
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#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
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#define HAS_DPT(dev_priv) (DISPLAY_VER(dev_priv) >= 13)
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#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
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#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
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#define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
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#define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
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#define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
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#define HAS_CDCLK_SQUASH(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
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#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
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#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
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#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
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#define HAS_PSR_HW_TRACKING(dev_priv) \
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(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
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#define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12)
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#define HAS_TRANSCODER(dev_priv, trans) ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
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#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
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#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
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#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
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#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
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#define HAS_DMC(dev_priv) (RUNTIME_INFO(dev_priv)->has_dmc)
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#define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
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#define HAS_DSC(__i915) (RUNTIME_INFO(__i915)->has_dsc)
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#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
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#define HAS_HECI_PXP(dev_priv) \
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(INTEL_INFO(dev_priv)->has_heci_pxp)
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#define HAS_HECI_GSCFI(dev_priv) \
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(INTEL_INFO(dev_priv)->has_heci_gscfi)
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#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
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#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
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#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
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#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
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#define HAS_OA_BPC_REPORTING(dev_priv) \
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(INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
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#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
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(INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
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#define HAS_OAM(dev_priv) \
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(INTEL_INFO(dev_priv)->has_oam)
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/*
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* Set this flag, when platform requires 64K GTT page sizes or larger for
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* device local memory access.
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*/
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#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
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#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
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#define HAS_SAGV(dev_priv) (DISPLAY_VER(dev_priv) >= 9 && !IS_LP(dev_priv))
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#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
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#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
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#define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list)
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/*
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* Platform has the dedicated compression control state for each lmem surfaces
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* stored in lmem to support the 3D and media compression formats.
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*/
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#define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)
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#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
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#define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
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#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
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#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
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#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
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#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
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#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
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/* DPF == dynamic parity feature */
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#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
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#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
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2 : HAS_L3_DPF(dev_priv))
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#define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
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#define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
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#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
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#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
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/* Only valid when HAS_DISPLAY() is true */
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#define INTEL_DISPLAY_ENABLED(dev_priv) \
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(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), \
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!(dev_priv)->params.disable_display && \
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!intel_opregion_headless_sku(dev_priv))
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#define HAS_GUC_DEPRIVILEGE(dev_priv) \
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(INTEL_INFO(dev_priv)->has_guc_deprivilege)
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#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
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IS_ALDERLAKE_S(dev_priv))
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#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
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#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
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#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
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#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
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GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
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/* intel_device_info.c */
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static inline struct intel_device_info *
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mkwrite_device_info(struct drm_i915_private *dev_priv)
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{
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return (struct intel_device_info *)INTEL_INFO(dev_priv);
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}
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#endif
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