400 lines
12 KiB
C
400 lines
12 KiB
C
/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef __INTEL_UNCORE_H__
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#define __INTEL_UNCORE_H__
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#include <linux/spinlock.h>
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#include <linux/notifier.h>
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#include <linux/hrtimer.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include "i915_reg.h"
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struct drm_i915_private;
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struct i915_runtime_pm;
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struct intel_uncore;
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enum forcewake_domain_id {
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FW_DOMAIN_ID_RENDER = 0,
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FW_DOMAIN_ID_BLITTER,
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FW_DOMAIN_ID_MEDIA,
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FW_DOMAIN_ID_MEDIA_VDBOX0,
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FW_DOMAIN_ID_MEDIA_VDBOX1,
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FW_DOMAIN_ID_MEDIA_VDBOX2,
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FW_DOMAIN_ID_MEDIA_VDBOX3,
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FW_DOMAIN_ID_MEDIA_VEBOX0,
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FW_DOMAIN_ID_MEDIA_VEBOX1,
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FW_DOMAIN_ID_COUNT
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};
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enum forcewake_domains {
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FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),
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FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER),
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FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA),
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FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
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FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
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FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
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FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
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FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
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FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
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FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1
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};
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struct intel_uncore_funcs {
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void (*force_wake_get)(struct intel_uncore *uncore,
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enum forcewake_domains domains);
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void (*force_wake_put)(struct intel_uncore *uncore,
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enum forcewake_domains domains);
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u8 (*mmio_readb)(struct intel_uncore *uncore,
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i915_reg_t r, bool trace);
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u16 (*mmio_readw)(struct intel_uncore *uncore,
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i915_reg_t r, bool trace);
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u32 (*mmio_readl)(struct intel_uncore *uncore,
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i915_reg_t r, bool trace);
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u64 (*mmio_readq)(struct intel_uncore *uncore,
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i915_reg_t r, bool trace);
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void (*mmio_writeb)(struct intel_uncore *uncore,
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i915_reg_t r, u8 val, bool trace);
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void (*mmio_writew)(struct intel_uncore *uncore,
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i915_reg_t r, u16 val, bool trace);
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void (*mmio_writel)(struct intel_uncore *uncore,
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i915_reg_t r, u32 val, bool trace);
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};
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struct intel_forcewake_range {
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u32 start;
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u32 end;
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enum forcewake_domains domains;
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};
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struct intel_uncore {
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void __iomem *regs;
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struct i915_runtime_pm *rpm;
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spinlock_t lock; /** lock is also taken in irq contexts. */
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unsigned int flags;
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#define UNCORE_HAS_FORCEWAKE BIT(0)
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#define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
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#define UNCORE_HAS_DBG_UNCLAIMED BIT(2)
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#define UNCORE_HAS_FIFO BIT(3)
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const struct intel_forcewake_range *fw_domains_table;
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unsigned int fw_domains_table_entries;
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struct notifier_block pmic_bus_access_nb;
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struct intel_uncore_funcs funcs;
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unsigned int fifo_count;
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enum forcewake_domains fw_domains;
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enum forcewake_domains fw_domains_active;
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enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
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struct intel_uncore_forcewake_domain {
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enum forcewake_domain_id id;
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enum forcewake_domains mask;
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unsigned int wake_count;
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bool active;
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struct hrtimer timer;
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u32 __iomem *reg_set;
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u32 __iomem *reg_ack;
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} fw_domain[FW_DOMAIN_ID_COUNT];
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struct {
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unsigned int count;
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int saved_mmio_check;
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int saved_mmio_debug;
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} user_forcewake;
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int unclaimed_mmio_check;
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};
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/* Iterate over initialised fw domains */
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#define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \
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for (tmp__ = (mask__); \
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tmp__ ? (domain__ = &(uncore__)->fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
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#define for_each_fw_domain(domain__, uncore__, tmp__) \
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for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__)
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static inline struct intel_uncore *
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forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
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{
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return container_of(d, struct intel_uncore, fw_domain[d->id]);
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}
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static inline bool
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intel_uncore_has_forcewake(const struct intel_uncore *uncore)
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{
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return uncore->flags & UNCORE_HAS_FORCEWAKE;
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}
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static inline bool
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intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore)
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{
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return uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED;
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}
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static inline bool
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intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore)
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{
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return uncore->flags & UNCORE_HAS_DBG_UNCLAIMED;
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}
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static inline bool
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intel_uncore_has_fifo(const struct intel_uncore *uncore)
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{
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return uncore->flags & UNCORE_HAS_FIFO;
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}
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void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
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void intel_uncore_init_early(struct intel_uncore *uncore);
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int intel_uncore_init_mmio(struct intel_uncore *uncore);
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void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore);
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bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
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bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
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void intel_uncore_fini_mmio(struct intel_uncore *uncore);
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void intel_uncore_suspend(struct intel_uncore *uncore);
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void intel_uncore_resume_early(struct intel_uncore *uncore);
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void intel_uncore_runtime_resume(struct intel_uncore *uncore);
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void assert_forcewakes_inactive(struct intel_uncore *uncore);
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void assert_forcewakes_active(struct intel_uncore *uncore,
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enum forcewake_domains fw_domains);
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const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
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enum forcewake_domains
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intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
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i915_reg_t reg, unsigned int op);
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#define FW_REG_READ (1)
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#define FW_REG_WRITE (2)
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void intel_uncore_forcewake_get(struct intel_uncore *uncore,
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enum forcewake_domains domains);
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void intel_uncore_forcewake_put(struct intel_uncore *uncore,
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enum forcewake_domains domains);
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/* Like above but the caller must manage the uncore.lock itself.
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* Must be used with I915_READ_FW and friends.
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*/
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void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
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enum forcewake_domains domains);
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void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
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enum forcewake_domains domains);
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void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
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void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
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int __intel_wait_for_register(struct intel_uncore *uncore,
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i915_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int fast_timeout_us,
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unsigned int slow_timeout_ms,
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u32 *out_value);
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static inline int
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intel_wait_for_register(struct intel_uncore *uncore,
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i915_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int timeout_ms)
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{
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return __intel_wait_for_register(uncore, reg, mask, value, 2,
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timeout_ms, NULL);
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}
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int __intel_wait_for_register_fw(struct intel_uncore *uncore,
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i915_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int fast_timeout_us,
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unsigned int slow_timeout_ms,
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u32 *out_value);
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static inline int
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intel_wait_for_register_fw(struct intel_uncore *uncore,
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i915_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int timeout_ms)
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{
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return __intel_wait_for_register_fw(uncore, reg, mask, value,
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2, timeout_ms, NULL);
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}
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/* register access functions */
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#define __raw_read(x__, s__) \
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static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
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i915_reg_t reg) \
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{ \
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return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
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}
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#define __raw_write(x__, s__) \
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static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
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i915_reg_t reg, u##x__ val) \
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{ \
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write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
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}
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__raw_read(8, b)
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__raw_read(16, w)
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__raw_read(32, l)
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__raw_read(64, q)
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__raw_write(8, b)
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__raw_write(16, w)
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__raw_write(32, l)
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__raw_write(64, q)
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#undef __raw_read
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#undef __raw_write
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#define __uncore_read(name__, x__, s__, trace__) \
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static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
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i915_reg_t reg) \
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{ \
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return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \
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}
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#define __uncore_write(name__, x__, s__, trace__) \
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static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
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i915_reg_t reg, u##x__ val) \
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{ \
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uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \
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}
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__uncore_read(read8, 8, b, true)
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__uncore_read(read16, 16, w, true)
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__uncore_read(read, 32, l, true)
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__uncore_read(read16_notrace, 16, w, false)
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__uncore_read(read_notrace, 32, l, false)
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__uncore_write(write8, 8, b, true)
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__uncore_write(write16, 16, w, true)
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__uncore_write(write, 32, l, true)
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__uncore_write(write_notrace, 32, l, false)
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/* Be very careful with read/write 64-bit values. On 32-bit machines, they
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* will be implemented using 2 32-bit writes in an arbitrary order with
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* an arbitrary delay between them. This can cause the hardware to
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* act upon the intermediate value, possibly leading to corruption and
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* machine death. For this reason we do not support I915_WRITE64, or
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* uncore->funcs.mmio_writeq.
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*
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* When reading a 64-bit value as two 32-bit values, the delay may cause
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* the two reads to mismatch, e.g. a timestamp overflowing. Also note that
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* occasionally a 64-bit register does not actually support a full readq
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* and must be read using two 32-bit reads.
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*
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* You have been warned.
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*/
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__uncore_read(read64, 64, q, true)
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static inline u64
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intel_uncore_read64_2x32(struct intel_uncore *uncore,
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i915_reg_t lower_reg, i915_reg_t upper_reg)
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{
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u32 upper, lower, old_upper, loop = 0;
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upper = intel_uncore_read(uncore, upper_reg);
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do {
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old_upper = upper;
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lower = intel_uncore_read(uncore, lower_reg);
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upper = intel_uncore_read(uncore, upper_reg);
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} while (upper != old_upper && loop++ < 2);
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return (u64)upper << 32 | lower;
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}
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#define intel_uncore_posting_read(...) ((void)intel_uncore_read_notrace(__VA_ARGS__))
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#define intel_uncore_posting_read16(...) ((void)intel_uncore_read16_notrace(__VA_ARGS__))
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#undef __uncore_read
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#undef __uncore_write
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/* These are untraced mmio-accessors that are only valid to be used inside
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* critical sections, such as inside IRQ handlers, where forcewake is explicitly
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* controlled.
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*
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* Think twice, and think again, before using these.
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*
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* As an example, these accessors can possibly be used between:
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*
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* spin_lock_irq(&uncore->lock);
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* intel_uncore_forcewake_get__locked();
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*
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* and
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*
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* intel_uncore_forcewake_put__locked();
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* spin_unlock_irq(&uncore->lock);
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*
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*
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* Note: some registers may not need forcewake held, so
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* intel_uncore_forcewake_{get,put} can be omitted, see
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* intel_uncore_forcewake_for_reg().
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*
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* Certain architectures will die if the same cacheline is concurrently accessed
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* by different clients (e.g. on Ivybridge). Access to registers should
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* therefore generally be serialised, by either the dev_priv->uncore.lock or
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* a more localised lock guarding all access to that bank of registers.
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*/
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#define intel_uncore_read_fw(...) __raw_uncore_read32(__VA_ARGS__)
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#define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__)
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#define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__)
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#define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__))
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static inline void intel_uncore_rmw(struct intel_uncore *uncore,
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i915_reg_t reg, u32 clear, u32 set)
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{
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u32 val;
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val = intel_uncore_read(uncore, reg);
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val &= ~clear;
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val |= set;
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intel_uncore_write(uncore, reg, val);
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}
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static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
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i915_reg_t reg, u32 clear, u32 set)
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{
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u32 val;
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val = intel_uncore_read_fw(uncore, reg);
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val &= ~clear;
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val |= set;
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intel_uncore_write_fw(uncore, reg, val);
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}
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#define raw_reg_read(base, reg) \
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readl(base + i915_mmio_reg_offset(reg))
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#define raw_reg_write(base, reg, value) \
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writel(value, base + i915_mmio_reg_offset(reg))
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#endif /* !__INTEL_UNCORE_H__ */
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