500 lines
14 KiB
C
500 lines
14 KiB
C
/*
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* Copyright (C) 2013 Advanced Micro Devices, Inc.
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*
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* Author: Steven Kinney <Steven.Kinney@amd.com>
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* Author: Suravee Suthikulpanit <Suraveee.Suthikulpanit@amd.com>
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*
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* Perf: amd_iommu - AMD IOMMU Performance Counter PMU implementation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/perf_event.h>
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#include <linux/module.h>
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#include <linux/cpumask.h>
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#include <linux/slab.h>
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#include "perf_event.h"
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#include "perf_event_amd_iommu.h"
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#define COUNTER_SHIFT 16
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#define _GET_BANK(ev) ((u8)(ev->hw.extra_reg.reg >> 8))
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#define _GET_CNTR(ev) ((u8)(ev->hw.extra_reg.reg))
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/* iommu pmu config masks */
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#define _GET_CSOURCE(ev) ((ev->hw.config & 0xFFULL))
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#define _GET_DEVID(ev) ((ev->hw.config >> 8) & 0xFFFFULL)
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#define _GET_PASID(ev) ((ev->hw.config >> 24) & 0xFFFFULL)
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#define _GET_DOMID(ev) ((ev->hw.config >> 40) & 0xFFFFULL)
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#define _GET_DEVID_MASK(ev) ((ev->hw.extra_reg.config) & 0xFFFFULL)
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#define _GET_PASID_MASK(ev) ((ev->hw.extra_reg.config >> 16) & 0xFFFFULL)
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#define _GET_DOMID_MASK(ev) ((ev->hw.extra_reg.config >> 32) & 0xFFFFULL)
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static struct perf_amd_iommu __perf_iommu;
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struct perf_amd_iommu {
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struct pmu pmu;
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u8 max_banks;
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u8 max_counters;
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u64 cntr_assign_mask;
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raw_spinlock_t lock;
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const struct attribute_group *attr_groups[4];
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};
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#define format_group attr_groups[0]
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#define cpumask_group attr_groups[1]
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#define events_group attr_groups[2]
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#define null_group attr_groups[3]
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/*---------------------------------------------
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* sysfs format attributes
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*---------------------------------------------*/
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PMU_FORMAT_ATTR(csource, "config:0-7");
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PMU_FORMAT_ATTR(devid, "config:8-23");
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PMU_FORMAT_ATTR(pasid, "config:24-39");
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PMU_FORMAT_ATTR(domid, "config:40-55");
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PMU_FORMAT_ATTR(devid_mask, "config1:0-15");
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PMU_FORMAT_ATTR(pasid_mask, "config1:16-31");
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PMU_FORMAT_ATTR(domid_mask, "config1:32-47");
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static struct attribute *iommu_format_attrs[] = {
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&format_attr_csource.attr,
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&format_attr_devid.attr,
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&format_attr_pasid.attr,
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&format_attr_domid.attr,
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&format_attr_devid_mask.attr,
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&format_attr_pasid_mask.attr,
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&format_attr_domid_mask.attr,
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NULL,
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};
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static struct attribute_group amd_iommu_format_group = {
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.name = "format",
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.attrs = iommu_format_attrs,
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};
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/*---------------------------------------------
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* sysfs events attributes
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*---------------------------------------------*/
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struct amd_iommu_event_desc {
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struct kobj_attribute attr;
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const char *event;
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};
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static ssize_t _iommu_event_show(struct kobject *kobj,
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struct kobj_attribute *attr, char *buf)
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{
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struct amd_iommu_event_desc *event =
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container_of(attr, struct amd_iommu_event_desc, attr);
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return sprintf(buf, "%s\n", event->event);
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}
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#define AMD_IOMMU_EVENT_DESC(_name, _event) \
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{ \
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.attr = __ATTR(_name, 0444, _iommu_event_show, NULL), \
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.event = _event, \
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}
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static struct amd_iommu_event_desc amd_iommu_v2_event_descs[] = {
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AMD_IOMMU_EVENT_DESC(mem_pass_untrans, "csource=0x01"),
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AMD_IOMMU_EVENT_DESC(mem_pass_pretrans, "csource=0x02"),
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AMD_IOMMU_EVENT_DESC(mem_pass_excl, "csource=0x03"),
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AMD_IOMMU_EVENT_DESC(mem_target_abort, "csource=0x04"),
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AMD_IOMMU_EVENT_DESC(mem_trans_total, "csource=0x05"),
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AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pte_hit, "csource=0x06"),
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AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pte_mis, "csource=0x07"),
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AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pde_hit, "csource=0x08"),
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AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pde_mis, "csource=0x09"),
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AMD_IOMMU_EVENT_DESC(mem_dte_hit, "csource=0x0a"),
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AMD_IOMMU_EVENT_DESC(mem_dte_mis, "csource=0x0b"),
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AMD_IOMMU_EVENT_DESC(page_tbl_read_tot, "csource=0x0c"),
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AMD_IOMMU_EVENT_DESC(page_tbl_read_nst, "csource=0x0d"),
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AMD_IOMMU_EVENT_DESC(page_tbl_read_gst, "csource=0x0e"),
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AMD_IOMMU_EVENT_DESC(int_dte_hit, "csource=0x0f"),
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AMD_IOMMU_EVENT_DESC(int_dte_mis, "csource=0x10"),
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AMD_IOMMU_EVENT_DESC(cmd_processed, "csource=0x11"),
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AMD_IOMMU_EVENT_DESC(cmd_processed_inv, "csource=0x12"),
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AMD_IOMMU_EVENT_DESC(tlb_inv, "csource=0x13"),
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{ /* end: all zeroes */ },
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};
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/*---------------------------------------------
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* sysfs cpumask attributes
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*---------------------------------------------*/
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static cpumask_t iommu_cpumask;
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static ssize_t _iommu_cpumask_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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return cpumap_print_to_pagebuf(true, buf, &iommu_cpumask);
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}
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static DEVICE_ATTR(cpumask, S_IRUGO, _iommu_cpumask_show, NULL);
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static struct attribute *iommu_cpumask_attrs[] = {
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&dev_attr_cpumask.attr,
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NULL,
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};
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static struct attribute_group amd_iommu_cpumask_group = {
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.attrs = iommu_cpumask_attrs,
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};
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/*---------------------------------------------*/
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static int get_next_avail_iommu_bnk_cntr(struct perf_amd_iommu *perf_iommu)
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{
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unsigned long flags;
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int shift, bank, cntr, retval;
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int max_banks = perf_iommu->max_banks;
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int max_cntrs = perf_iommu->max_counters;
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raw_spin_lock_irqsave(&perf_iommu->lock, flags);
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for (bank = 0, shift = 0; bank < max_banks; bank++) {
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for (cntr = 0; cntr < max_cntrs; cntr++) {
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shift = bank + (bank*3) + cntr;
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if (perf_iommu->cntr_assign_mask & (1ULL<<shift)) {
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continue;
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} else {
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perf_iommu->cntr_assign_mask |= (1ULL<<shift);
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retval = ((u16)((u16)bank<<8) | (u8)(cntr));
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goto out;
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}
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}
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}
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retval = -ENOSPC;
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out:
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raw_spin_unlock_irqrestore(&perf_iommu->lock, flags);
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return retval;
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}
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static int clear_avail_iommu_bnk_cntr(struct perf_amd_iommu *perf_iommu,
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u8 bank, u8 cntr)
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{
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unsigned long flags;
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int max_banks, max_cntrs;
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int shift = 0;
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max_banks = perf_iommu->max_banks;
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max_cntrs = perf_iommu->max_counters;
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if ((bank > max_banks) || (cntr > max_cntrs))
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return -EINVAL;
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shift = bank + cntr + (bank*3);
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raw_spin_lock_irqsave(&perf_iommu->lock, flags);
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perf_iommu->cntr_assign_mask &= ~(1ULL<<shift);
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raw_spin_unlock_irqrestore(&perf_iommu->lock, flags);
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return 0;
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}
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static int perf_iommu_event_init(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct perf_amd_iommu *perf_iommu;
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u64 config, config1;
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/* test the event attr type check for PMU enumeration */
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if (event->attr.type != event->pmu->type)
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return -ENOENT;
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/*
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* IOMMU counters are shared across all cores.
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* Therefore, it does not support per-process mode.
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* Also, it does not support event sampling mode.
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*/
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if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
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return -EINVAL;
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/* IOMMU counters do not have usr/os/guest/host bits */
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if (event->attr.exclude_user || event->attr.exclude_kernel ||
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event->attr.exclude_host || event->attr.exclude_guest)
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return -EINVAL;
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if (event->cpu < 0)
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return -EINVAL;
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perf_iommu = &__perf_iommu;
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if (event->pmu != &perf_iommu->pmu)
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return -ENOENT;
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if (perf_iommu) {
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config = event->attr.config;
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config1 = event->attr.config1;
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} else {
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return -EINVAL;
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}
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/* integrate with iommu base devid (0000), assume one iommu */
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perf_iommu->max_banks =
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amd_iommu_pc_get_max_banks(IOMMU_BASE_DEVID);
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perf_iommu->max_counters =
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amd_iommu_pc_get_max_counters(IOMMU_BASE_DEVID);
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if ((perf_iommu->max_banks == 0) || (perf_iommu->max_counters == 0))
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return -EINVAL;
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/* update the hw_perf_event struct with the iommu config data */
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hwc->config = config;
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hwc->extra_reg.config = config1;
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return 0;
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}
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static void perf_iommu_enable_event(struct perf_event *ev)
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{
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u8 csource = _GET_CSOURCE(ev);
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u16 devid = _GET_DEVID(ev);
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u64 reg = 0ULL;
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reg = csource;
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amd_iommu_pc_get_set_reg_val(devid,
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_GET_BANK(ev), _GET_CNTR(ev) ,
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IOMMU_PC_COUNTER_SRC_REG, ®, true);
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reg = 0ULL | devid | (_GET_DEVID_MASK(ev) << 32);
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if (reg)
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reg |= (1UL << 31);
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amd_iommu_pc_get_set_reg_val(devid,
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_GET_BANK(ev), _GET_CNTR(ev) ,
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IOMMU_PC_DEVID_MATCH_REG, ®, true);
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reg = 0ULL | _GET_PASID(ev) | (_GET_PASID_MASK(ev) << 32);
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if (reg)
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reg |= (1UL << 31);
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amd_iommu_pc_get_set_reg_val(devid,
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_GET_BANK(ev), _GET_CNTR(ev) ,
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IOMMU_PC_PASID_MATCH_REG, ®, true);
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reg = 0ULL | _GET_DOMID(ev) | (_GET_DOMID_MASK(ev) << 32);
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if (reg)
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reg |= (1UL << 31);
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amd_iommu_pc_get_set_reg_val(devid,
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_GET_BANK(ev), _GET_CNTR(ev) ,
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IOMMU_PC_DOMID_MATCH_REG, ®, true);
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}
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static void perf_iommu_disable_event(struct perf_event *event)
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{
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u64 reg = 0ULL;
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amd_iommu_pc_get_set_reg_val(_GET_DEVID(event),
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_GET_BANK(event), _GET_CNTR(event),
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IOMMU_PC_COUNTER_SRC_REG, ®, true);
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}
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static void perf_iommu_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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pr_debug("perf: amd_iommu:perf_iommu_start\n");
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if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
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return;
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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if (flags & PERF_EF_RELOAD) {
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u64 prev_raw_count = local64_read(&hwc->prev_count);
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amd_iommu_pc_get_set_reg_val(_GET_DEVID(event),
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_GET_BANK(event), _GET_CNTR(event),
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IOMMU_PC_COUNTER_REG, &prev_raw_count, true);
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}
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perf_iommu_enable_event(event);
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perf_event_update_userpage(event);
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}
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static void perf_iommu_read(struct perf_event *event)
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{
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u64 count = 0ULL;
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u64 prev_raw_count = 0ULL;
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u64 delta = 0ULL;
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struct hw_perf_event *hwc = &event->hw;
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pr_debug("perf: amd_iommu:perf_iommu_read\n");
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amd_iommu_pc_get_set_reg_val(_GET_DEVID(event),
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_GET_BANK(event), _GET_CNTR(event),
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IOMMU_PC_COUNTER_REG, &count, false);
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/* IOMMU pc counter register is only 48 bits */
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count &= 0xFFFFFFFFFFFFULL;
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prev_raw_count = local64_read(&hwc->prev_count);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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count) != prev_raw_count)
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return;
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/* Handling 48-bit counter overflowing */
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delta = (count << COUNTER_SHIFT) - (prev_raw_count << COUNTER_SHIFT);
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delta >>= COUNTER_SHIFT;
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local64_add(delta, &event->count);
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}
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static void perf_iommu_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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u64 config;
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pr_debug("perf: amd_iommu:perf_iommu_stop\n");
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if (hwc->state & PERF_HES_UPTODATE)
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return;
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perf_iommu_disable_event(event);
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WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
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hwc->state |= PERF_HES_STOPPED;
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if (hwc->state & PERF_HES_UPTODATE)
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return;
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config = hwc->config;
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perf_iommu_read(event);
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hwc->state |= PERF_HES_UPTODATE;
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}
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static int perf_iommu_add(struct perf_event *event, int flags)
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{
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int retval;
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struct perf_amd_iommu *perf_iommu =
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container_of(event->pmu, struct perf_amd_iommu, pmu);
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pr_debug("perf: amd_iommu:perf_iommu_add\n");
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event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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/* request an iommu bank/counter */
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retval = get_next_avail_iommu_bnk_cntr(perf_iommu);
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if (retval != -ENOSPC)
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event->hw.extra_reg.reg = (u16)retval;
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else
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return retval;
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if (flags & PERF_EF_START)
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perf_iommu_start(event, PERF_EF_RELOAD);
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return 0;
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}
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static void perf_iommu_del(struct perf_event *event, int flags)
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{
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struct perf_amd_iommu *perf_iommu =
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container_of(event->pmu, struct perf_amd_iommu, pmu);
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pr_debug("perf: amd_iommu:perf_iommu_del\n");
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perf_iommu_stop(event, PERF_EF_UPDATE);
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/* clear the assigned iommu bank/counter */
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clear_avail_iommu_bnk_cntr(perf_iommu,
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_GET_BANK(event),
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_GET_CNTR(event));
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perf_event_update_userpage(event);
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}
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static __init int _init_events_attrs(struct perf_amd_iommu *perf_iommu)
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{
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struct attribute **attrs;
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struct attribute_group *attr_group;
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int i = 0, j;
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while (amd_iommu_v2_event_descs[i].attr.attr.name)
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i++;
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attr_group = kzalloc(sizeof(struct attribute *)
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* (i + 1) + sizeof(*attr_group), GFP_KERNEL);
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if (!attr_group)
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return -ENOMEM;
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attrs = (struct attribute **)(attr_group + 1);
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for (j = 0; j < i; j++)
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attrs[j] = &amd_iommu_v2_event_descs[j].attr.attr;
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attr_group->name = "events";
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attr_group->attrs = attrs;
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perf_iommu->events_group = attr_group;
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return 0;
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}
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static __init void amd_iommu_pc_exit(void)
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{
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if (__perf_iommu.events_group != NULL) {
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kfree(__perf_iommu.events_group);
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__perf_iommu.events_group = NULL;
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}
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}
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static __init int _init_perf_amd_iommu(
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struct perf_amd_iommu *perf_iommu, char *name)
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{
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int ret;
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raw_spin_lock_init(&perf_iommu->lock);
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/* Init format attributes */
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perf_iommu->format_group = &amd_iommu_format_group;
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/* Init cpumask attributes to only core 0 */
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cpumask_set_cpu(0, &iommu_cpumask);
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perf_iommu->cpumask_group = &amd_iommu_cpumask_group;
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/* Init events attributes */
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if (_init_events_attrs(perf_iommu) != 0)
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pr_err("perf: amd_iommu: Only support raw events.\n");
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/* Init null attributes */
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perf_iommu->null_group = NULL;
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perf_iommu->pmu.attr_groups = perf_iommu->attr_groups;
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ret = perf_pmu_register(&perf_iommu->pmu, name, -1);
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if (ret) {
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pr_err("perf: amd_iommu: Failed to initialized.\n");
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amd_iommu_pc_exit();
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} else {
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pr_info("perf: amd_iommu: Detected. (%d banks, %d counters/bank)\n",
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amd_iommu_pc_get_max_banks(IOMMU_BASE_DEVID),
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amd_iommu_pc_get_max_counters(IOMMU_BASE_DEVID));
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct perf_amd_iommu __perf_iommu = {
|
|
.pmu = {
|
|
.event_init = perf_iommu_event_init,
|
|
.add = perf_iommu_add,
|
|
.del = perf_iommu_del,
|
|
.start = perf_iommu_start,
|
|
.stop = perf_iommu_stop,
|
|
.read = perf_iommu_read,
|
|
},
|
|
.max_banks = 0x00,
|
|
.max_counters = 0x00,
|
|
.cntr_assign_mask = 0ULL,
|
|
.format_group = NULL,
|
|
.cpumask_group = NULL,
|
|
.events_group = NULL,
|
|
.null_group = NULL,
|
|
};
|
|
|
|
static __init int amd_iommu_pc_init(void)
|
|
{
|
|
/* Make sure the IOMMU PC resource is available */
|
|
if (!amd_iommu_pc_supported())
|
|
return -ENODEV;
|
|
|
|
_init_perf_amd_iommu(&__perf_iommu, "amd_iommu");
|
|
|
|
return 0;
|
|
}
|
|
|
|
device_initcall(amd_iommu_pc_init);
|