442 lines
15 KiB
C
442 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#ifndef __LINUX_MTD_SPI_NOR_INTERNAL_H
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#define __LINUX_MTD_SPI_NOR_INTERNAL_H
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#include "sfdp.h"
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#define SPI_NOR_MAX_ID_LEN 6
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enum spi_nor_option_flags {
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SNOR_F_USE_FSR = BIT(0),
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SNOR_F_HAS_SR_TB = BIT(1),
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SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
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SNOR_F_READY_XSR_RDY = BIT(3),
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SNOR_F_USE_CLSR = BIT(4),
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SNOR_F_BROKEN_RESET = BIT(5),
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SNOR_F_4B_OPCODES = BIT(6),
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SNOR_F_HAS_4BAIT = BIT(7),
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SNOR_F_HAS_LOCK = BIT(8),
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SNOR_F_HAS_16BIT_SR = BIT(9),
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SNOR_F_NO_READ_CR = BIT(10),
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SNOR_F_HAS_SR_TB_BIT6 = BIT(11),
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SNOR_F_HAS_4BIT_BP = BIT(12),
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SNOR_F_HAS_SR_BP3_BIT6 = BIT(13),
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};
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struct spi_nor_read_command {
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u8 num_mode_clocks;
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u8 num_wait_states;
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u8 opcode;
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enum spi_nor_protocol proto;
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};
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struct spi_nor_pp_command {
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u8 opcode;
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enum spi_nor_protocol proto;
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};
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enum spi_nor_read_command_index {
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SNOR_CMD_READ,
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SNOR_CMD_READ_FAST,
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SNOR_CMD_READ_1_1_1_DTR,
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/* Dual SPI */
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SNOR_CMD_READ_1_1_2,
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SNOR_CMD_READ_1_2_2,
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SNOR_CMD_READ_2_2_2,
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SNOR_CMD_READ_1_2_2_DTR,
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/* Quad SPI */
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SNOR_CMD_READ_1_1_4,
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SNOR_CMD_READ_1_4_4,
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SNOR_CMD_READ_4_4_4,
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SNOR_CMD_READ_1_4_4_DTR,
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/* Octal SPI */
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SNOR_CMD_READ_1_1_8,
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SNOR_CMD_READ_1_8_8,
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SNOR_CMD_READ_8_8_8,
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SNOR_CMD_READ_1_8_8_DTR,
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SNOR_CMD_READ_MAX
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};
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enum spi_nor_pp_command_index {
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SNOR_CMD_PP,
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/* Quad SPI */
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SNOR_CMD_PP_1_1_4,
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SNOR_CMD_PP_1_4_4,
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SNOR_CMD_PP_4_4_4,
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/* Octal SPI */
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SNOR_CMD_PP_1_1_8,
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SNOR_CMD_PP_1_8_8,
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SNOR_CMD_PP_8_8_8,
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SNOR_CMD_PP_MAX
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};
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/**
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* struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
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* @size: the size of the sector/block erased by the erase type.
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* JEDEC JESD216B imposes erase sizes to be a power of 2.
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* @size_shift: @size is a power of 2, the shift is stored in
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* @size_shift.
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* @size_mask: the size mask based on @size_shift.
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* @opcode: the SPI command op code to erase the sector/block.
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* @idx: Erase Type index as sorted in the Basic Flash Parameter
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* Table. It will be used to synchronize the supported
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* Erase Types with the ones identified in the SFDP
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* optional tables.
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*/
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struct spi_nor_erase_type {
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u32 size;
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u32 size_shift;
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u32 size_mask;
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u8 opcode;
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u8 idx;
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};
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/**
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* struct spi_nor_erase_command - Used for non-uniform erases
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* The structure is used to describe a list of erase commands to be executed
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* once we validate that the erase can be performed. The elements in the list
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* are run-length encoded.
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* @list: for inclusion into the list of erase commands.
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* @count: how many times the same erase command should be
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* consecutively used.
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* @size: the size of the sector/block erased by the command.
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* @opcode: the SPI command op code to erase the sector/block.
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*/
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struct spi_nor_erase_command {
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struct list_head list;
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u32 count;
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u32 size;
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u8 opcode;
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};
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/**
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* struct spi_nor_erase_region - Structure to describe a SPI NOR erase region
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* @offset: the offset in the data array of erase region start.
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* LSB bits are used as a bitmask encoding flags to
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* determine if this region is overlaid, if this region is
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* the last in the SPI NOR flash memory and to indicate
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* all the supported erase commands inside this region.
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* The erase types are sorted in ascending order with the
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* smallest Erase Type size being at BIT(0).
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* @size: the size of the region in bytes.
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*/
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struct spi_nor_erase_region {
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u64 offset;
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u64 size;
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};
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#define SNOR_ERASE_TYPE_MAX 4
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#define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0)
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#define SNOR_LAST_REGION BIT(4)
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#define SNOR_OVERLAID_REGION BIT(5)
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#define SNOR_ERASE_FLAGS_MAX 6
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#define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0)
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/**
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* struct spi_nor_erase_map - Structure to describe the SPI NOR erase map
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* @regions: array of erase regions. The regions are consecutive in
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* address space. Walking through the regions is done
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* incrementally.
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* @uniform_region: a pre-allocated erase region for SPI NOR with a uniform
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* sector size (legacy implementation).
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* @erase_type: an array of erase types shared by all the regions.
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* The erase types are sorted in ascending order, with the
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* smallest Erase Type size being the first member in the
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* erase_type array.
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* @uniform_erase_type: bitmask encoding erase types that can erase the
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* entire memory. This member is completed at init by
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* uniform and non-uniform SPI NOR flash memories if they
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* support at least one erase type that can erase the
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* entire memory.
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*/
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struct spi_nor_erase_map {
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struct spi_nor_erase_region *regions;
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struct spi_nor_erase_region uniform_region;
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struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX];
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u8 uniform_erase_type;
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};
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/**
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* struct spi_nor_locking_ops - SPI NOR locking methods
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* @lock: lock a region of the SPI NOR.
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* @unlock: unlock a region of the SPI NOR.
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* @is_locked: check if a region of the SPI NOR is completely locked
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*/
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struct spi_nor_locking_ops {
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int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
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int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
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int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
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};
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/**
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* struct spi_nor_flash_parameter - SPI NOR flash parameters and settings.
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* Includes legacy flash parameters and settings that can be overwritten
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* by the spi_nor_fixups hooks, or dynamically when parsing the JESD216
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* Serial Flash Discoverable Parameters (SFDP) tables.
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*
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* @size: the flash memory density in bytes.
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* @page_size: the page size of the SPI NOR flash memory.
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* @hwcaps: describes the read and page program hardware
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* capabilities.
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* @reads: read capabilities ordered by priority: the higher index
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* in the array, the higher priority.
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* @page_programs: page program capabilities ordered by priority: the
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* higher index in the array, the higher priority.
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* @erase_map: the erase map parsed from the SFDP Sector Map Parameter
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* Table.
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* @quad_enable: enables/disables SPI NOR Quad mode.
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* @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
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* @convert_addr: converts an absolute address into something the flash
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* will understand. Particularly useful when pagesize is
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* not a power-of-2.
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* @setup: configures the SPI NOR memory. Useful for SPI NOR
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* flashes that have peculiarities to the SPI NOR standard
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* e.g. different opcodes, specific address calculation,
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* page size, etc.
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* @locking_ops: SPI NOR locking methods.
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*/
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struct spi_nor_flash_parameter {
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u64 size;
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u32 page_size;
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struct spi_nor_hwcaps hwcaps;
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struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
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struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
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struct spi_nor_erase_map erase_map;
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int (*quad_enable)(struct spi_nor *nor, bool enable);
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int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
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u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
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int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
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const struct spi_nor_locking_ops *locking_ops;
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};
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/**
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* struct spi_nor_fixups - SPI NOR fixup hooks
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* @default_init: called after default flash parameters init. Used to tweak
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* flash parameters when information provided by the flash_info
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* table is incomplete or wrong.
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* @post_bfpt: called after the BFPT table has been parsed
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* @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
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* that do not support RDSFDP). Typically used to tweak various
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* parameters that could not be extracted by other means (i.e.
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* when information provided by the SFDP/flash_info tables are
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* incomplete or wrong).
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*
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* Those hooks can be used to tweak the SPI NOR configuration when the SFDP
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* table is broken or not available.
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*/
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struct spi_nor_fixups {
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void (*default_init)(struct spi_nor *nor);
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int (*post_bfpt)(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params);
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void (*post_sfdp)(struct spi_nor *nor);
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};
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struct flash_info {
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char *name;
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/*
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* This array stores the ID bytes.
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* The first three bytes are the JEDIC ID.
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* JEDEC ID zero means "no ID" (mostly older chips).
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*/
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u8 id[SPI_NOR_MAX_ID_LEN];
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u8 id_len;
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/* The size listed here is what works with SPINOR_OP_SE, which isn't
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* necessarily called a "sector" by the vendor.
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*/
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unsigned sector_size;
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u16 n_sectors;
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u16 page_size;
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u16 addr_width;
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u32 flags;
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#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
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#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
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#define SST_WRITE BIT(2) /* use SST byte programming */
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#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
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#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
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#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
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#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
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#define USE_FSR BIT(7) /* use flag status register */
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#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
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#define SPI_NOR_HAS_TB BIT(9) /*
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* Flash SR has Top/Bottom (TB) protect
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* bit. Must be used with
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* SPI_NOR_HAS_LOCK.
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*/
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#define SPI_NOR_XSR_RDY BIT(10) /*
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* S3AN flashes have specific opcode to
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* read the status register.
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*/
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#define SPI_NOR_4B_OPCODES BIT(11) /*
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* Use dedicated 4byte address op codes
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* to support memory size above 128Mib.
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*/
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#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
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#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
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#define USE_CLSR BIT(14) /* use CLSR command */
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#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
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#define SPI_NOR_TB_SR_BIT6 BIT(16) /*
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* Top/Bottom (TB) is bit 6 of
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* status register. Must be used with
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* SPI_NOR_HAS_TB.
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*/
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#define SPI_NOR_4BIT_BP BIT(17) /*
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* Flash SR has 4 bit fields (BP0-3)
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* for block protection.
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*/
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#define SPI_NOR_BP3_SR_BIT6 BIT(18) /*
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* BP3 is bit 6 of status register.
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* Must be used with SPI_NOR_4BIT_BP.
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*/
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/* Part specific fixup hooks. */
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const struct spi_nor_fixups *fixups;
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};
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/* Used when the "_ext_id" is two bytes at most */
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#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff, \
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((_ext_id) >> 8) & 0xff, \
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(_ext_id) & 0xff, \
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}, \
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.id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
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.sector_size = (_sector_size), \
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.n_sectors = (_n_sectors), \
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.page_size = 256, \
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.flags = (_flags),
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#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff, \
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((_ext_id) >> 16) & 0xff, \
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((_ext_id) >> 8) & 0xff, \
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(_ext_id) & 0xff, \
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}, \
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.id_len = 6, \
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.sector_size = (_sector_size), \
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.n_sectors = (_n_sectors), \
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.page_size = 256, \
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.flags = (_flags),
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#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
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.sector_size = (_sector_size), \
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.n_sectors = (_n_sectors), \
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.page_size = (_page_size), \
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.addr_width = (_addr_width), \
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.flags = (_flags),
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#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff \
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}, \
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.id_len = 3, \
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.sector_size = (8*_page_size), \
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.n_sectors = (_n_sectors), \
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.page_size = _page_size, \
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.addr_width = 3, \
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.flags = SPI_NOR_NO_FR | SPI_NOR_XSR_RDY,
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/**
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* struct spi_nor_manufacturer - SPI NOR manufacturer object
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* @name: manufacturer name
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* @parts: array of parts supported by this manufacturer
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* @nparts: number of entries in the parts array
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* @fixups: hooks called at various points in time during spi_nor_scan()
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*/
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struct spi_nor_manufacturer {
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const char *name;
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const struct flash_info *parts;
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unsigned int nparts;
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const struct spi_nor_fixups *fixups;
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};
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/* Manufacturer drivers. */
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extern const struct spi_nor_manufacturer spi_nor_atmel;
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extern const struct spi_nor_manufacturer spi_nor_catalyst;
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extern const struct spi_nor_manufacturer spi_nor_eon;
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extern const struct spi_nor_manufacturer spi_nor_esmt;
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extern const struct spi_nor_manufacturer spi_nor_everspin;
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extern const struct spi_nor_manufacturer spi_nor_fujitsu;
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extern const struct spi_nor_manufacturer spi_nor_gigadevice;
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extern const struct spi_nor_manufacturer spi_nor_intel;
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extern const struct spi_nor_manufacturer spi_nor_issi;
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extern const struct spi_nor_manufacturer spi_nor_macronix;
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extern const struct spi_nor_manufacturer spi_nor_micron;
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extern const struct spi_nor_manufacturer spi_nor_st;
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extern const struct spi_nor_manufacturer spi_nor_spansion;
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extern const struct spi_nor_manufacturer spi_nor_sst;
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extern const struct spi_nor_manufacturer spi_nor_winbond;
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extern const struct spi_nor_manufacturer spi_nor_xilinx;
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extern const struct spi_nor_manufacturer spi_nor_xmc;
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int spi_nor_write_enable(struct spi_nor *nor);
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int spi_nor_write_disable(struct spi_nor *nor);
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int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable);
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int spi_nor_write_ear(struct spi_nor *nor, u8 ear);
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int spi_nor_wait_till_ready(struct spi_nor *nor);
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int spi_nor_lock_and_prep(struct spi_nor *nor);
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void spi_nor_unlock_and_unprep(struct spi_nor *nor);
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int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor, bool enable);
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int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor, bool enable);
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int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor, bool enable);
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int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr);
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ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
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u8 *buf);
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ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
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const u8 *buf);
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int spi_nor_hwcaps_read2cmd(u32 hwcaps);
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u8 spi_nor_convert_3to4_read(u8 opcode);
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void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
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enum spi_nor_protocol proto);
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void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
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u8 opcode);
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struct spi_nor_erase_region *
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spi_nor_region_next(struct spi_nor_erase_region *region);
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void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
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u8 erase_mask, u64 flash_size);
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int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params);
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static struct spi_nor __maybe_unused *mtd_to_spi_nor(struct mtd_info *mtd)
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{
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return mtd->priv;
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}
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#endif /* __LINUX_MTD_SPI_NOR_INTERNAL_H */
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