128 lines
3.3 KiB
C
128 lines
3.3 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2014 Intel Corporation
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*/
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#ifndef __GEN8_ENGINE_CS_H__
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#define __GEN8_ENGINE_CS_H__
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#include <linux/string.h>
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#include <linux/types.h>
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#include "i915_gem.h" /* GEM_BUG_ON */
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#include "intel_gpu_commands.h"
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struct i915_request;
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int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode);
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int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode);
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int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode);
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int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode);
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int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode);
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int gen8_emit_init_breadcrumb(struct i915_request *rq);
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int gen8_emit_bb_start_noarb(struct i915_request *rq,
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u64 offset, u32 len,
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const unsigned int flags);
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int gen8_emit_bb_start(struct i915_request *rq,
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u64 offset, u32 len,
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const unsigned int flags);
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u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
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u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
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u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
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u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
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u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
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static inline u32 *
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__gen8_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
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{
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memset(batch, 0, 6 * sizeof(u32));
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batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0;
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batch[1] = flags1;
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batch[2] = offset;
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return batch + 6;
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}
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static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
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{
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return __gen8_emit_pipe_control(batch, 0, flags, offset);
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}
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static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
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{
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return __gen8_emit_pipe_control(batch, flags0, flags1, offset);
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}
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static inline u32 *
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__gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1)
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{
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*cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
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*cs++ = flags1 | PIPE_CONTROL_QW_WRITE;
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*cs++ = offset;
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*cs++ = 0;
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*cs++ = value;
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*cs++ = 0; /* We're thrashing one extra dword. */
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return cs;
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}
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static inline u32*
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gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
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{
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/* We're using qword write, offset should be aligned to 8 bytes. */
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GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
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return __gen8_emit_write_rcs(cs,
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value,
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gtt_offset,
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0,
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flags | PIPE_CONTROL_GLOBAL_GTT_IVB);
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}
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static inline u32*
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gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
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{
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/* We're using qword write, offset should be aligned to 8 bytes. */
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GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
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return __gen8_emit_write_rcs(cs,
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value,
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gtt_offset,
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flags0,
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flags1 | PIPE_CONTROL_GLOBAL_GTT_IVB);
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}
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static inline u32 *
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__gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
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{
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*cs++ = (MI_FLUSH_DW + 1) | flags;
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*cs++ = gtt_offset;
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*cs++ = 0;
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*cs++ = value;
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return cs;
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}
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static inline u32 *
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gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
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{
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/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
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GEM_BUG_ON(gtt_offset & (1 << 5));
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/* Offset should be aligned to 8 bytes for both (QW/DW) write types */
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GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
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return __gen8_emit_flush_dw(cs,
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value,
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gtt_offset | MI_FLUSH_DW_USE_GTT,
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flags | MI_FLUSH_DW_OP_STOREDW);
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}
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#endif /* __GEN8_ENGINE_CS_H__ */
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