244 lines
5.8 KiB
C
244 lines
5.8 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Setting up the clock on the MIPS boards.
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*/
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#include <linux/types.h>
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#include <linux/i8253.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/math64.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/mips-gic.h>
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#include <linux/timex.h>
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#include <linux/mc146818rtc.h>
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#include <asm/cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/hardirq.h>
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#include <asm/irq.h>
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#include <asm/div64.h>
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#include <asm/setup.h>
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#include <asm/time.h>
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#include <asm/mc146818-time.h>
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#include <asm/msc01_ic.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/maltaint.h>
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static int mips_cpu_timer_irq;
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static int mips_cpu_perf_irq;
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extern int cp0_perfcount_irq;
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static unsigned int gic_frequency;
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static void mips_timer_dispatch(void)
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{
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do_IRQ(mips_cpu_timer_irq);
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}
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static void mips_perf_dispatch(void)
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{
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do_IRQ(mips_cpu_perf_irq);
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}
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static unsigned int freqround(unsigned int freq, unsigned int amount)
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{
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freq += amount;
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freq -= freq % (amount*2);
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return freq;
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}
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/*
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* Estimate CPU and GIC frequencies.
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*/
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static void __init estimate_frequencies(void)
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{
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unsigned long flags;
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unsigned int count, start;
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unsigned char secs1, secs2, ctrl;
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int secs;
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cycle_t giccount = 0, gicstart = 0;
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#if defined(CONFIG_KVM_GUEST) && CONFIG_KVM_GUEST_TIMER_FREQ
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mips_hpt_frequency = CONFIG_KVM_GUEST_TIMER_FREQ * 1000000;
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return;
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#endif
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local_irq_save(flags);
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if (gic_present)
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gic_start_count();
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/*
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* Read counters exactly on rising edge of update flag.
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* This helps get an accurate reading under virtualisation.
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*/
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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start = read_c0_count();
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if (gic_present)
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gicstart = gic_read_count();
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/* Wait for falling edge before reading RTC. */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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secs1 = CMOS_READ(RTC_SECONDS);
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/* Read counters again exactly on rising edge of update flag. */
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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count = read_c0_count();
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if (gic_present)
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giccount = gic_read_count();
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/* Wait for falling edge before reading RTC again. */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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secs2 = CMOS_READ(RTC_SECONDS);
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ctrl = CMOS_READ(RTC_CONTROL);
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local_irq_restore(flags);
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if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
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secs1 = bcd2bin(secs1);
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secs2 = bcd2bin(secs2);
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}
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secs = secs2 - secs1;
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if (secs < 1)
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secs += 60;
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count -= start;
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count /= secs;
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mips_hpt_frequency = count;
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if (gic_present) {
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giccount = div_u64(giccount - gicstart, secs);
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gic_frequency = giccount;
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}
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}
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void read_persistent_clock(struct timespec *ts)
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{
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ts->tv_sec = mc146818_get_cmos_time();
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ts->tv_nsec = 0;
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}
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int get_c0_fdc_int(void)
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{
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/*
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* Some cores claim the FDC is routable through the GIC, but it doesn't
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* actually seem to be connected for those Malta bitstreams.
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*/
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switch (current_cpu_type()) {
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case CPU_INTERAPTIV:
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case CPU_PROAPTIV:
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return -1;
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};
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if (cpu_has_veic)
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return -1;
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else if (gic_present)
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return gic_get_c0_fdc_int();
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else if (cp0_fdc_irq >= 0)
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return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
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else
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return -1;
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}
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int get_c0_perfcount_int(void)
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{
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if (cpu_has_veic) {
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set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
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mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
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} else if (gic_present) {
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mips_cpu_perf_irq = gic_get_c0_perfcount_int();
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} else if (cp0_perfcount_irq >= 0) {
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mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
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} else {
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mips_cpu_perf_irq = -1;
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}
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return mips_cpu_perf_irq;
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}
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EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
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unsigned int get_c0_compare_int(void)
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{
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if (cpu_has_veic) {
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set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
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mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
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} else if (gic_present) {
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mips_cpu_timer_irq = gic_get_c0_compare_int();
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} else {
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mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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}
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return mips_cpu_timer_irq;
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}
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static void __init init_rtc(void)
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{
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unsigned char freq, ctrl;
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/* Set 32KHz time base if not already set */
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freq = CMOS_READ(RTC_FREQ_SELECT);
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if ((freq & RTC_DIV_CTL) != RTC_REF_CLCK_32KHZ)
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CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
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/* Ensure SET bit is clear so RTC can run */
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ctrl = CMOS_READ(RTC_CONTROL);
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if (ctrl & RTC_SET)
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CMOS_WRITE(ctrl & ~RTC_SET, RTC_CONTROL);
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}
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void __init plat_time_init(void)
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{
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unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
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unsigned int freq;
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init_rtc();
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estimate_frequencies();
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freq = mips_hpt_frequency;
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if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
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(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
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freq *= 2;
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freq = freqround(freq, 5000);
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printk("CPU frequency %d.%02d MHz\n", freq/1000000,
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(freq%1000000)*100/1000000);
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mips_scroll_message();
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#ifdef CONFIG_I8253
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/* Only Malta has a PIT. */
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setup_pit_timer();
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#endif
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#ifdef CONFIG_MIPS_GIC
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if (gic_present) {
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freq = freqround(gic_frequency, 5000);
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printk("GIC frequency %d.%02d MHz\n", freq/1000000,
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(freq%1000000)*100/1000000);
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#ifdef CONFIG_CLKSRC_MIPS_GIC
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gic_clocksource_init(gic_frequency);
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#endif
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}
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#endif
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}
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