504 lines
17 KiB
ArmAsm
504 lines
17 KiB
ArmAsm
########################################################################
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# Implement fast SHA-256 with AVX1 instructions. (x86_64)
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#
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# Copyright (C) 2013 Intel Corporation.
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#
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# Authors:
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# James Guilford <james.guilford@intel.com>
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# Kirk Yap <kirk.s.yap@intel.com>
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# Tim Chen <tim.c.chen@linux.intel.com>
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#
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# This software is available to you under a choice of one of two
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# licenses. You may choose to be licensed under the terms of the GNU
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# General Public License (GPL) Version 2, available from the file
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# COPYING in the main directory of this source tree, or the
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# OpenIB.org BSD license below:
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#
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# Redistribution and use in source and binary forms, with or
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# without modification, are permitted provided that the following
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# conditions are met:
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#
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# - Redistributions of source code must retain the above
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# copyright notice, this list of conditions and the following
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# disclaimer.
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#
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# - Redistributions in binary form must reproduce the above
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# copyright notice, this list of conditions and the following
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# disclaimer in the documentation and/or other materials
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# provided with the distribution.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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########################################################################
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#
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# This code is described in an Intel White-Paper:
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# "Fast SHA-256 Implementations on Intel Architecture Processors"
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#
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# To find it, surf to http://www.intel.com/p/en_US/embedded
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# and search for that title.
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#
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########################################################################
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# This code schedules 1 block at a time, with 4 lanes per block
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########################################################################
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#ifdef CONFIG_AS_AVX
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#include <linux/linkage.h>
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## assume buffers not aligned
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#define VMOVDQ vmovdqu
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################################ Define Macros
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# addm [mem], reg
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# Add reg to mem using reg-mem add and store
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.macro addm p1 p2
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add \p1, \p2
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mov \p2, \p1
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.endm
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.macro MY_ROR p1 p2
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shld $(32-(\p1)), \p2, \p2
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.endm
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################################
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# COPY_XMM_AND_BSWAP xmm, [mem], byte_flip_mask
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# Load xmm with mem and byte swap each dword
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.macro COPY_XMM_AND_BSWAP p1 p2 p3
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VMOVDQ \p2, \p1
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vpshufb \p3, \p1, \p1
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.endm
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################################
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X0 = %xmm4
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X1 = %xmm5
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X2 = %xmm6
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X3 = %xmm7
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XTMP0 = %xmm0
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XTMP1 = %xmm1
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XTMP2 = %xmm2
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XTMP3 = %xmm3
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XTMP4 = %xmm8
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XFER = %xmm9
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XTMP5 = %xmm11
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SHUF_00BA = %xmm10 # shuffle xBxA -> 00BA
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SHUF_DC00 = %xmm12 # shuffle xDxC -> DC00
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BYTE_FLIP_MASK = %xmm13
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NUM_BLKS = %rdx # 3rd arg
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INP = %rsi # 2nd arg
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CTX = %rdi # 1st arg
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SRND = %rsi # clobbers INP
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c = %ecx
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d = %r8d
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e = %edx
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TBL = %rbp
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a = %eax
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b = %ebx
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f = %r9d
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g = %r10d
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h = %r11d
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y0 = %r13d
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y1 = %r14d
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y2 = %r15d
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_INP_END_SIZE = 8
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_INP_SIZE = 8
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_XFER_SIZE = 16
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_XMM_SAVE_SIZE = 0
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_INP_END = 0
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_INP = _INP_END + _INP_END_SIZE
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_XFER = _INP + _INP_SIZE
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_XMM_SAVE = _XFER + _XFER_SIZE
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STACK_SIZE = _XMM_SAVE + _XMM_SAVE_SIZE
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# rotate_Xs
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# Rotate values of symbols X0...X3
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.macro rotate_Xs
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X_ = X0
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X0 = X1
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X1 = X2
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X2 = X3
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X3 = X_
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.endm
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# ROTATE_ARGS
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# Rotate values of symbols a...h
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.macro ROTATE_ARGS
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TMP_ = h
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h = g
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g = f
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f = e
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e = d
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d = c
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c = b
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b = a
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a = TMP_
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.endm
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.macro FOUR_ROUNDS_AND_SCHED
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## compute s0 four at a time and s1 two at a time
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## compute W[-16] + W[-7] 4 at a time
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mov e, y0 # y0 = e
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MY_ROR (25-11), y0 # y0 = e >> (25-11)
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mov a, y1 # y1 = a
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vpalignr $4, X2, X3, XTMP0 # XTMP0 = W[-7]
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MY_ROR (22-13), y1 # y1 = a >> (22-13)
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xor e, y0 # y0 = e ^ (e >> (25-11))
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mov f, y2 # y2 = f
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MY_ROR (11-6), y0 # y0 = (e >> (11-6)) ^ (e >> (25-6))
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xor a, y1 # y1 = a ^ (a >> (22-13)
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xor g, y2 # y2 = f^g
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vpaddd X0, XTMP0, XTMP0 # XTMP0 = W[-7] + W[-16]
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xor e, y0 # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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and e, y2 # y2 = (f^g)&e
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MY_ROR (13-2), y1 # y1 = (a >> (13-2)) ^ (a >> (22-2))
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## compute s0
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vpalignr $4, X0, X1, XTMP1 # XTMP1 = W[-15]
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xor a, y1 # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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MY_ROR 6, y0 # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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xor g, y2 # y2 = CH = ((f^g)&e)^g
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MY_ROR 2, y1 # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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add y0, y2 # y2 = S1 + CH
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add _XFER(%rsp), y2 # y2 = k + w + S1 + CH
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mov a, y0 # y0 = a
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add y2, h # h = h + S1 + CH + k + w
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mov a, y2 # y2 = a
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vpsrld $7, XTMP1, XTMP2
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or c, y0 # y0 = a|c
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add h, d # d = d + h + S1 + CH + k + w
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and c, y2 # y2 = a&c
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vpslld $(32-7), XTMP1, XTMP3
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and b, y0 # y0 = (a|c)&b
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add y1, h # h = h + S1 + CH + k + w + S0
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vpor XTMP2, XTMP3, XTMP3 # XTMP1 = W[-15] MY_ROR 7
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or y2, y0 # y0 = MAJ = (a|c)&b)|(a&c)
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add y0, h # h = h + S1 + CH + k + w + S0 + MAJ
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ROTATE_ARGS
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mov e, y0 # y0 = e
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mov a, y1 # y1 = a
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MY_ROR (25-11), y0 # y0 = e >> (25-11)
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xor e, y0 # y0 = e ^ (e >> (25-11))
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mov f, y2 # y2 = f
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MY_ROR (22-13), y1 # y1 = a >> (22-13)
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vpsrld $18, XTMP1, XTMP2 #
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xor a, y1 # y1 = a ^ (a >> (22-13)
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MY_ROR (11-6), y0 # y0 = (e >> (11-6)) ^ (e >> (25-6))
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xor g, y2 # y2 = f^g
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vpsrld $3, XTMP1, XTMP4 # XTMP4 = W[-15] >> 3
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MY_ROR (13-2), y1 # y1 = (a >> (13-2)) ^ (a >> (22-2))
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xor e, y0 # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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and e, y2 # y2 = (f^g)&e
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MY_ROR 6, y0 # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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vpslld $(32-18), XTMP1, XTMP1
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xor a, y1 # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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xor g, y2 # y2 = CH = ((f^g)&e)^g
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vpxor XTMP1, XTMP3, XTMP3 #
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add y0, y2 # y2 = S1 + CH
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add (1*4 + _XFER)(%rsp), y2 # y2 = k + w + S1 + CH
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MY_ROR 2, y1 # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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vpxor XTMP2, XTMP3, XTMP3 # XTMP1 = W[-15] MY_ROR 7 ^ W[-15] MY_ROR
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mov a, y0 # y0 = a
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add y2, h # h = h + S1 + CH + k + w
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mov a, y2 # y2 = a
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vpxor XTMP4, XTMP3, XTMP1 # XTMP1 = s0
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or c, y0 # y0 = a|c
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add h, d # d = d + h + S1 + CH + k + w
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and c, y2 # y2 = a&c
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## compute low s1
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vpshufd $0b11111010, X3, XTMP2 # XTMP2 = W[-2] {BBAA}
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and b, y0 # y0 = (a|c)&b
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add y1, h # h = h + S1 + CH + k + w + S0
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vpaddd XTMP1, XTMP0, XTMP0 # XTMP0 = W[-16] + W[-7] + s0
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or y2, y0 # y0 = MAJ = (a|c)&b)|(a&c)
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add y0, h # h = h + S1 + CH + k + w + S0 + MAJ
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ROTATE_ARGS
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mov e, y0 # y0 = e
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mov a, y1 # y1 = a
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MY_ROR (25-11), y0 # y0 = e >> (25-11)
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xor e, y0 # y0 = e ^ (e >> (25-11))
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MY_ROR (22-13), y1 # y1 = a >> (22-13)
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mov f, y2 # y2 = f
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xor a, y1 # y1 = a ^ (a >> (22-13)
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MY_ROR (11-6), y0 # y0 = (e >> (11-6)) ^ (e >> (25-6))
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vpsrld $10, XTMP2, XTMP4 # XTMP4 = W[-2] >> 10 {BBAA}
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xor g, y2 # y2 = f^g
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vpsrlq $19, XTMP2, XTMP3 # XTMP3 = W[-2] MY_ROR 19 {xBxA}
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xor e, y0 # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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and e, y2 # y2 = (f^g)&e
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vpsrlq $17, XTMP2, XTMP2 # XTMP2 = W[-2] MY_ROR 17 {xBxA}
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MY_ROR (13-2), y1 # y1 = (a >> (13-2)) ^ (a >> (22-2))
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xor a, y1 # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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xor g, y2 # y2 = CH = ((f^g)&e)^g
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MY_ROR 6, y0 # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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vpxor XTMP3, XTMP2, XTMP2 #
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add y0, y2 # y2 = S1 + CH
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MY_ROR 2, y1 # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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add (2*4 + _XFER)(%rsp), y2 # y2 = k + w + S1 + CH
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vpxor XTMP2, XTMP4, XTMP4 # XTMP4 = s1 {xBxA}
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mov a, y0 # y0 = a
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add y2, h # h = h + S1 + CH + k + w
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mov a, y2 # y2 = a
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vpshufb SHUF_00BA, XTMP4, XTMP4 # XTMP4 = s1 {00BA}
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or c, y0 # y0 = a|c
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add h, d # d = d + h + S1 + CH + k + w
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and c, y2 # y2 = a&c
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vpaddd XTMP4, XTMP0, XTMP0 # XTMP0 = {..., ..., W[1], W[0]}
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and b, y0 # y0 = (a|c)&b
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add y1, h # h = h + S1 + CH + k + w + S0
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## compute high s1
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vpshufd $0b01010000, XTMP0, XTMP2 # XTMP2 = W[-2] {DDCC}
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or y2, y0 # y0 = MAJ = (a|c)&b)|(a&c)
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add y0, h # h = h + S1 + CH + k + w + S0 + MAJ
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ROTATE_ARGS
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mov e, y0 # y0 = e
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MY_ROR (25-11), y0 # y0 = e >> (25-11)
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mov a, y1 # y1 = a
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MY_ROR (22-13), y1 # y1 = a >> (22-13)
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xor e, y0 # y0 = e ^ (e >> (25-11))
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mov f, y2 # y2 = f
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MY_ROR (11-6), y0 # y0 = (e >> (11-6)) ^ (e >> (25-6))
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vpsrld $10, XTMP2, XTMP5 # XTMP5 = W[-2] >> 10 {DDCC}
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xor a, y1 # y1 = a ^ (a >> (22-13)
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xor g, y2 # y2 = f^g
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vpsrlq $19, XTMP2, XTMP3 # XTMP3 = W[-2] MY_ROR 19 {xDxC}
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xor e, y0 # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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and e, y2 # y2 = (f^g)&e
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MY_ROR (13-2), y1 # y1 = (a >> (13-2)) ^ (a >> (22-2))
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vpsrlq $17, XTMP2, XTMP2 # XTMP2 = W[-2] MY_ROR 17 {xDxC}
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xor a, y1 # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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MY_ROR 6, y0 # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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xor g, y2 # y2 = CH = ((f^g)&e)^g
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vpxor XTMP3, XTMP2, XTMP2
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MY_ROR 2, y1 # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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add y0, y2 # y2 = S1 + CH
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add (3*4 + _XFER)(%rsp), y2 # y2 = k + w + S1 + CH
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vpxor XTMP2, XTMP5, XTMP5 # XTMP5 = s1 {xDxC}
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mov a, y0 # y0 = a
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add y2, h # h = h + S1 + CH + k + w
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mov a, y2 # y2 = a
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vpshufb SHUF_DC00, XTMP5, XTMP5 # XTMP5 = s1 {DC00}
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or c, y0 # y0 = a|c
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add h, d # d = d + h + S1 + CH + k + w
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and c, y2 # y2 = a&c
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vpaddd XTMP0, XTMP5, X0 # X0 = {W[3], W[2], W[1], W[0]}
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and b, y0 # y0 = (a|c)&b
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add y1, h # h = h + S1 + CH + k + w + S0
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or y2, y0 # y0 = MAJ = (a|c)&b)|(a&c)
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add y0, h # h = h + S1 + CH + k + w + S0 + MAJ
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ROTATE_ARGS
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rotate_Xs
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.endm
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## input is [rsp + _XFER + %1 * 4]
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.macro DO_ROUND round
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mov e, y0 # y0 = e
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MY_ROR (25-11), y0 # y0 = e >> (25-11)
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mov a, y1 # y1 = a
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xor e, y0 # y0 = e ^ (e >> (25-11))
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MY_ROR (22-13), y1 # y1 = a >> (22-13)
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mov f, y2 # y2 = f
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xor a, y1 # y1 = a ^ (a >> (22-13)
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MY_ROR (11-6), y0 # y0 = (e >> (11-6)) ^ (e >> (25-6))
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xor g, y2 # y2 = f^g
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xor e, y0 # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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MY_ROR (13-2), y1 # y1 = (a >> (13-2)) ^ (a >> (22-2))
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and e, y2 # y2 = (f^g)&e
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xor a, y1 # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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MY_ROR 6, y0 # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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xor g, y2 # y2 = CH = ((f^g)&e)^g
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add y0, y2 # y2 = S1 + CH
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MY_ROR 2, y1 # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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offset = \round * 4 + _XFER #
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add offset(%rsp), y2 # y2 = k + w + S1 + CH
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mov a, y0 # y0 = a
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add y2, h # h = h + S1 + CH + k + w
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mov a, y2 # y2 = a
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or c, y0 # y0 = a|c
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add h, d # d = d + h + S1 + CH + k + w
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and c, y2 # y2 = a&c
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and b, y0 # y0 = (a|c)&b
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add y1, h # h = h + S1 + CH + k + w + S0
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or y2, y0 # y0 = MAJ = (a|c)&b)|(a&c)
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add y0, h # h = h + S1 + CH + k + w + S0 + MAJ
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ROTATE_ARGS
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.endm
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########################################################################
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## void sha256_transform_avx(void *input_data, UINT32 digest[8], UINT64 num_blks)
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## arg 1 : pointer to digest
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## arg 2 : pointer to input data
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## arg 3 : Num blocks
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########################################################################
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.text
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ENTRY(sha256_transform_avx)
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.align 32
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pushq %rbx
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pushq %rbp
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pushq %r13
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pushq %r14
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pushq %r15
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pushq %r12
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mov %rsp, %r12
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subq $STACK_SIZE, %rsp # allocate stack space
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and $~15, %rsp # align stack pointer
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shl $6, NUM_BLKS # convert to bytes
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jz done_hash
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add INP, NUM_BLKS # pointer to end of data
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mov NUM_BLKS, _INP_END(%rsp)
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## load initial digest
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mov 4*0(CTX), a
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mov 4*1(CTX), b
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mov 4*2(CTX), c
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mov 4*3(CTX), d
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mov 4*4(CTX), e
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mov 4*5(CTX), f
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mov 4*6(CTX), g
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mov 4*7(CTX), h
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vmovdqa PSHUFFLE_BYTE_FLIP_MASK(%rip), BYTE_FLIP_MASK
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vmovdqa _SHUF_00BA(%rip), SHUF_00BA
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vmovdqa _SHUF_DC00(%rip), SHUF_DC00
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loop0:
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lea K256(%rip), TBL
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## byte swap first 16 dwords
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COPY_XMM_AND_BSWAP X0, 0*16(INP), BYTE_FLIP_MASK
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COPY_XMM_AND_BSWAP X1, 1*16(INP), BYTE_FLIP_MASK
|
|
COPY_XMM_AND_BSWAP X2, 2*16(INP), BYTE_FLIP_MASK
|
|
COPY_XMM_AND_BSWAP X3, 3*16(INP), BYTE_FLIP_MASK
|
|
|
|
mov INP, _INP(%rsp)
|
|
|
|
## schedule 48 input dwords, by doing 3 rounds of 16 each
|
|
mov $3, SRND
|
|
.align 16
|
|
loop1:
|
|
vpaddd (TBL), X0, XFER
|
|
vmovdqa XFER, _XFER(%rsp)
|
|
FOUR_ROUNDS_AND_SCHED
|
|
|
|
vpaddd 1*16(TBL), X0, XFER
|
|
vmovdqa XFER, _XFER(%rsp)
|
|
FOUR_ROUNDS_AND_SCHED
|
|
|
|
vpaddd 2*16(TBL), X0, XFER
|
|
vmovdqa XFER, _XFER(%rsp)
|
|
FOUR_ROUNDS_AND_SCHED
|
|
|
|
vpaddd 3*16(TBL), X0, XFER
|
|
vmovdqa XFER, _XFER(%rsp)
|
|
add $4*16, TBL
|
|
FOUR_ROUNDS_AND_SCHED
|
|
|
|
sub $1, SRND
|
|
jne loop1
|
|
|
|
mov $2, SRND
|
|
loop2:
|
|
vpaddd (TBL), X0, XFER
|
|
vmovdqa XFER, _XFER(%rsp)
|
|
DO_ROUND 0
|
|
DO_ROUND 1
|
|
DO_ROUND 2
|
|
DO_ROUND 3
|
|
|
|
vpaddd 1*16(TBL), X1, XFER
|
|
vmovdqa XFER, _XFER(%rsp)
|
|
add $2*16, TBL
|
|
DO_ROUND 0
|
|
DO_ROUND 1
|
|
DO_ROUND 2
|
|
DO_ROUND 3
|
|
|
|
vmovdqa X2, X0
|
|
vmovdqa X3, X1
|
|
|
|
sub $1, SRND
|
|
jne loop2
|
|
|
|
addm (4*0)(CTX),a
|
|
addm (4*1)(CTX),b
|
|
addm (4*2)(CTX),c
|
|
addm (4*3)(CTX),d
|
|
addm (4*4)(CTX),e
|
|
addm (4*5)(CTX),f
|
|
addm (4*6)(CTX),g
|
|
addm (4*7)(CTX),h
|
|
|
|
mov _INP(%rsp), INP
|
|
add $64, INP
|
|
cmp _INP_END(%rsp), INP
|
|
jne loop0
|
|
|
|
done_hash:
|
|
|
|
mov %r12, %rsp
|
|
|
|
popq %r12
|
|
popq %r15
|
|
popq %r14
|
|
popq %r13
|
|
popq %rbp
|
|
popq %rbx
|
|
ret
|
|
ENDPROC(sha256_transform_avx)
|
|
|
|
.section .rodata.cst256.K256, "aM", @progbits, 256
|
|
.align 64
|
|
K256:
|
|
.long 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
|
|
.long 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
|
|
.long 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
|
|
.long 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
|
|
.long 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
|
|
.long 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
|
|
.long 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
|
|
.long 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
|
|
.long 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
|
|
.long 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
|
|
.long 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
|
|
.long 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
|
|
.long 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
|
|
.long 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
|
|
.long 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
|
|
.long 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
|
|
|
|
.section .rodata.cst16.PSHUFFLE_BYTE_FLIP_MASK, "aM", @progbits, 16
|
|
.align 16
|
|
PSHUFFLE_BYTE_FLIP_MASK:
|
|
.octa 0x0c0d0e0f08090a0b0405060700010203
|
|
|
|
.section .rodata.cst16._SHUF_00BA, "aM", @progbits, 16
|
|
.align 16
|
|
# shuffle xBxA -> 00BA
|
|
_SHUF_00BA:
|
|
.octa 0xFFFFFFFFFFFFFFFF0b0a090803020100
|
|
|
|
.section .rodata.cst16._SHUF_DC00, "aM", @progbits, 16
|
|
.align 16
|
|
# shuffle xDxC -> DC00
|
|
_SHUF_DC00:
|
|
.octa 0x0b0a090803020100FFFFFFFFFFFFFFFF
|
|
|
|
#endif
|