127 lines
2.4 KiB
C
127 lines
2.4 KiB
C
#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include "clk.h"
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#include "common.h"
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#include "hardware.h"
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/**
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* pll v1
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*
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* @clk_hw clock source
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* @parent the parent clock name
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* @base base address of pll registers
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*
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* PLL clock version 1, found on i.MX1/21/25/27/31/35
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*/
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#define MFN_BITS (10)
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#define MFN_SIGN (BIT(MFN_BITS - 1))
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#define MFN_MASK (MFN_SIGN - 1)
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struct clk_pllv1 {
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struct clk_hw hw;
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void __iomem *base;
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};
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#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
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static inline bool mfn_is_negative(unsigned int mfn)
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{
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return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN);
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}
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static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_pllv1 *pll = to_clk_pllv1(hw);
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long long ll;
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int mfn_abs;
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unsigned int mfi, mfn, mfd, pd;
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u32 reg;
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unsigned long rate;
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reg = readl(pll->base);
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/*
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* Get the resulting clock rate from a PLL register value and the input
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* frequency. PLLs with this register layout can be found on i.MX1,
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* i.MX21, i.MX27 and i,MX31
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*
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* mfi + mfn / (mfd + 1)
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* f = 2 * f_ref * --------------------
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* pd + 1
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*/
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mfi = (reg >> 10) & 0xf;
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mfn = reg & 0x3ff;
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mfd = (reg >> 16) & 0x3ff;
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pd = (reg >> 26) & 0xf;
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mfi = mfi <= 5 ? 5 : mfi;
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mfn_abs = mfn;
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/*
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* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
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* 2's complements number.
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* On i.MX27 the bit 9 is the sign bit.
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*/
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if (mfn_is_negative(mfn)) {
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if (cpu_is_mx27())
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mfn_abs = mfn & MFN_MASK;
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else
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mfn_abs = BIT(MFN_BITS) - mfn;
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}
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rate = parent_rate * 2;
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rate /= pd + 1;
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ll = (unsigned long long)rate * mfn_abs;
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do_div(ll, mfd + 1);
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if (mfn_is_negative(mfn))
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ll = -ll;
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ll = (rate * mfi) + ll;
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return ll;
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}
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static struct clk_ops clk_pllv1_ops = {
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.recalc_rate = clk_pllv1_recalc_rate,
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};
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struct clk *imx_clk_pllv1(const char *name, const char *parent,
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void __iomem *base)
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{
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struct clk_pllv1 *pll;
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struct clk *clk;
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struct clk_init_data init;
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pll = kmalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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pll->base = base;
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init.name = name;
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init.ops = &clk_pllv1_ops;
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init.flags = 0;
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init.parent_names = &parent;
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init.num_parents = 1;
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pll->hw.init = &init;
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clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(clk))
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kfree(pll);
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return clk;
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}
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