608 lines
18 KiB
C
608 lines
18 KiB
C
/* QLogic qed NIC Driver
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* Copyright (c) 2015 QLogic Corporation
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*
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* This software is available under the terms of the GNU General Public License
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#ifndef __COMMON_HSI__
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#define __COMMON_HSI__
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#define FW_MAJOR_VERSION 8
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#define FW_MINOR_VERSION 4
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#define FW_REVISION_VERSION 2
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#define FW_ENGINEERING_VERSION 0
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/***********************/
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/* COMMON HW CONSTANTS */
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/***********************/
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/* PCI functions */
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#define MAX_NUM_PORTS_K2 (4)
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#define MAX_NUM_PORTS_BB (2)
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#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2)
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#define MAX_NUM_PFS_K2 (16)
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#define MAX_NUM_PFS_BB (8)
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#define MAX_NUM_PFS (MAX_NUM_PFS_K2)
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#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
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#define MAX_NUM_VFS_K2 (192)
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#define MAX_NUM_VFS_BB (120)
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#define MAX_NUM_VFS (MAX_NUM_VFS_K2)
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#define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
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#define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS)
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#define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB)
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#define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS)
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#define MAX_NUM_VPORTS_K2 (208)
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#define MAX_NUM_VPORTS_BB (160)
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#define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2)
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#define MAX_NUM_L2_QUEUES_K2 (320)
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#define MAX_NUM_L2_QUEUES_BB (256)
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#define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2)
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/* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
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#define NUM_PHYS_TCS_4PORT_K2 (4)
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#define NUM_OF_PHYS_TCS (8)
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#define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1)
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#define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1)
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#define LB_TC (NUM_OF_PHYS_TCS)
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/* Num of possible traffic priority values */
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#define NUM_OF_PRIO (8)
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#define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
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#define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB)
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#define MAX_NUM_VOQS (MAX_NUM_VOQS_K2)
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#define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)
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/* CIDs */
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#define NUM_OF_CONNECTION_TYPES (8)
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#define NUM_OF_LCIDS (320)
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#define NUM_OF_LTIDS (320)
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/*****************/
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/* CDU CONSTANTS */
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/*****************/
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#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
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#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
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/*****************/
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/* DQ CONSTANTS */
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/*****************/
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/* DEMS */
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#define DQ_DEMS_LEGACY 0
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/* XCM agg val selection */
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#define DQ_XCM_AGG_VAL_SEL_WORD2 0
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#define DQ_XCM_AGG_VAL_SEL_WORD3 1
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#define DQ_XCM_AGG_VAL_SEL_WORD4 2
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#define DQ_XCM_AGG_VAL_SEL_WORD5 3
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#define DQ_XCM_AGG_VAL_SEL_REG3 4
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#define DQ_XCM_AGG_VAL_SEL_REG4 5
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#define DQ_XCM_AGG_VAL_SEL_REG5 6
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#define DQ_XCM_AGG_VAL_SEL_REG6 7
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/* XCM agg val selection */
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#define DQ_XCM_ETH_EDPM_NUM_BDS_CMD \
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DQ_XCM_AGG_VAL_SEL_WORD2
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#define DQ_XCM_ETH_TX_BD_CONS_CMD \
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DQ_XCM_AGG_VAL_SEL_WORD3
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#define DQ_XCM_CORE_TX_BD_CONS_CMD \
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DQ_XCM_AGG_VAL_SEL_WORD3
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#define DQ_XCM_ETH_TX_BD_PROD_CMD \
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DQ_XCM_AGG_VAL_SEL_WORD4
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#define DQ_XCM_CORE_TX_BD_PROD_CMD \
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DQ_XCM_AGG_VAL_SEL_WORD4
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#define DQ_XCM_CORE_SPQ_PROD_CMD \
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DQ_XCM_AGG_VAL_SEL_WORD4
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#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
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/* XCM agg counter flag selection */
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#define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
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#define DQ_XCM_AGG_FLG_SHIFT_BIT15 1
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#define DQ_XCM_AGG_FLG_SHIFT_CF12 2
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#define DQ_XCM_AGG_FLG_SHIFT_CF13 3
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#define DQ_XCM_AGG_FLG_SHIFT_CF18 4
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#define DQ_XCM_AGG_FLG_SHIFT_CF19 5
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#define DQ_XCM_AGG_FLG_SHIFT_CF22 6
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#define DQ_XCM_AGG_FLG_SHIFT_CF23 7
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/* XCM agg counter flag selection */
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#define DQ_XCM_ETH_DQ_CF_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF18)
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#define DQ_XCM_CORE_DQ_CF_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF18)
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#define DQ_XCM_ETH_TERMINATE_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF19)
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#define DQ_XCM_CORE_TERMINATE_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF19)
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#define DQ_XCM_ETH_SLOW_PATH_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF22)
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#define DQ_XCM_CORE_SLOW_PATH_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF22)
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#define DQ_XCM_ETH_TPH_EN_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF23)
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/*****************/
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/* QM CONSTANTS */
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/*****************/
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/* number of TX queues in the QM */
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#define MAX_QM_TX_QUEUES_K2 512
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#define MAX_QM_TX_QUEUES_BB 448
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#define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2
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/* number of Other queues in the QM */
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#define MAX_QM_OTHER_QUEUES_BB 64
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#define MAX_QM_OTHER_QUEUES_K2 128
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#define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2
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/* number of queues in a PF queue group */
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#define QM_PF_QUEUE_GROUP_SIZE 8
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/* base number of Tx PQs in the CM PQ representation.
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* should be used when storing PQ IDs in CM PQ registers and context
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*/
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#define CM_TX_PQ_BASE 0x200
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/* QM registers data */
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#define QM_LINE_CRD_REG_WIDTH 16
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#define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1))
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#define QM_BYTE_CRD_REG_WIDTH 24
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#define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1))
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#define QM_WFQ_CRD_REG_WIDTH 32
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#define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1))
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#define QM_RL_CRD_REG_WIDTH 32
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#define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1))
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/*****************/
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/* CAU CONSTANTS */
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/*****************/
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#define CAU_FSM_ETH_RX 0
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#define CAU_FSM_ETH_TX 1
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/* Number of Protocol Indices per Status Block */
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#define PIS_PER_SB 12
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#define CAU_HC_STOPPED_STATE 3
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#define CAU_HC_DISABLE_STATE 4
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#define CAU_HC_ENABLE_STATE 0
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/*****************/
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/* IGU CONSTANTS */
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/*****************/
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#define MAX_SB_PER_PATH_K2 (368)
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#define MAX_SB_PER_PATH_BB (288)
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#define MAX_TOT_SB_PER_PATH \
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MAX_SB_PER_PATH_K2
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#define MAX_SB_PER_PF_MIMD 129
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#define MAX_SB_PER_PF_SIMD 64
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#define MAX_SB_PER_VF 64
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/* Memory addresses on the BAR for the IGU Sub Block */
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#define IGU_MEM_BASE 0x0000
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#define IGU_MEM_MSIX_BASE 0x0000
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#define IGU_MEM_MSIX_UPPER 0x0101
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#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
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#define IGU_MEM_PBA_MSIX_BASE 0x0200
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#define IGU_MEM_PBA_MSIX_UPPER 0x0202
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#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
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#define IGU_CMD_INT_ACK_BASE 0x0400
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#define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \
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MAX_TOT_SB_PER_PATH - \
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1)
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#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
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#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
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#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1
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#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2
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#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3
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#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4
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#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5
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#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6
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#define IGU_CMD_PROD_UPD_BASE 0x0600
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#define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\
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MAX_TOT_SB_PER_PATH - \
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1)
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#define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
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/*****************/
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/* PXP CONSTANTS */
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/*****************/
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/* PTT and GTT */
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#define PXP_NUM_PF_WINDOWS 12
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#define PXP_PER_PF_ENTRY_SIZE 8
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#define PXP_NUM_GLOBAL_WINDOWS 243
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#define PXP_GLOBAL_ENTRY_SIZE 4
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#define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4
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#define PXP_PF_WINDOW_ADMIN_START 0
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#define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000
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#define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \
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PXP_PF_WINDOW_ADMIN_LENGTH - 1)
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#define PXP_PF_WINDOW_ADMIN_PER_PF_START 0
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#define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \
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PXP_PER_PF_ENTRY_SIZE)
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#define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \
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PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
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#define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200
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#define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \
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PXP_GLOBAL_ENTRY_SIZE)
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#define PXP_PF_WINDOW_ADMIN_GLOBAL_END \
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(PXP_PF_WINDOW_ADMIN_GLOBAL_START + \
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PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)
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#define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0
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#define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4
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#define PXP_PF_ME_OPAQUE_ADDR 0x1f8
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#define PXP_PF_ME_CONCRETE_ADDR 0x1fc
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#define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000
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#define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS
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#define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000
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#define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \
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(PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \
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PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE)
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#define PXP_EXTERNAL_BAR_PF_WINDOW_END \
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(PXP_EXTERNAL_BAR_PF_WINDOW_START + \
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PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1)
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#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \
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(PXP_EXTERNAL_BAR_PF_WINDOW_END + 1)
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#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS
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#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000
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#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \
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(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \
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PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE)
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#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \
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(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
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PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
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#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
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#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
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/* ILT Records */
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#define PXP_NUM_ILT_RECORDS_BB 7600
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#define PXP_NUM_ILT_RECORDS_K2 11000
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#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
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/******************/
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/* PBF CONSTANTS */
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/******************/
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/* Number of PBF command queue lines. Each line is 32B. */
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#define PBF_MAX_CMD_LINES 3328
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/* Number of BTB blocks. Each block is 256B. */
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#define BTB_MAX_BLOCKS 1440
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/*****************/
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/* PRS CONSTANTS */
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/*****************/
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/* Async data KCQ CQE */
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struct async_data {
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__le32 cid;
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__le16 itid;
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u8 error_code;
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u8 fw_debug_param;
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};
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struct regpair {
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__le32 lo;
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__le32 hi;
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};
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/* Event Data Union */
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union event_ring_data {
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u8 bytes[8];
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struct async_data async_info;
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};
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/* Event Ring Entry */
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struct event_ring_entry {
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u8 protocol_id;
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u8 opcode;
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__le16 reserved0;
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__le16 echo;
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u8 fw_return_code;
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u8 flags;
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#define EVENT_RING_ENTRY_ASYNC_MASK 0x1
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#define EVENT_RING_ENTRY_ASYNC_SHIFT 0
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#define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
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#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
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union event_ring_data data;
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};
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/* Multi function mode */
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enum mf_mode {
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SF,
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MF_OVLAN,
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MF_NPAR,
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MAX_MF_MODE
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};
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/* Per-protocol connection types */
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enum protocol_type {
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PROTOCOLID_RESERVED1,
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PROTOCOLID_RESERVED2,
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PROTOCOLID_RESERVED3,
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PROTOCOLID_CORE,
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PROTOCOLID_ETH,
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PROTOCOLID_RESERVED4,
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PROTOCOLID_RESERVED5,
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PROTOCOLID_PREROCE,
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PROTOCOLID_COMMON,
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PROTOCOLID_RESERVED6,
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MAX_PROTOCOL_TYPE
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};
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/* status block structure */
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struct cau_pi_entry {
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u32 prod;
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#define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
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#define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
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#define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
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#define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
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#define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
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#define CAU_PI_ENTRY_FSM_SEL_SHIFT 23
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#define CAU_PI_ENTRY_RESERVED_MASK 0xFF
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#define CAU_PI_ENTRY_RESERVED_SHIFT 24
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};
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/* status block structure */
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struct cau_sb_entry {
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u32 data;
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#define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
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#define CAU_SB_ENTRY_SB_PROD_SHIFT 0
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#define CAU_SB_ENTRY_STATE0_MASK 0xF
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#define CAU_SB_ENTRY_STATE0_SHIFT 24
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#define CAU_SB_ENTRY_STATE1_MASK 0xF
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#define CAU_SB_ENTRY_STATE1_SHIFT 28
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u32 params;
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#define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
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#define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
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#define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
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#define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
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#define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
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#define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14
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#define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
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#define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16
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#define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
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#define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18
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#define CAU_SB_ENTRY_VF_VALID_MASK 0x1
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#define CAU_SB_ENTRY_VF_VALID_SHIFT 26
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#define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
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#define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27
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#define CAU_SB_ENTRY_TPH_MASK 0x1
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#define CAU_SB_ENTRY_TPH_SHIFT 31
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};
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/* core doorbell data */
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struct core_db_data {
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u8 params;
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#define CORE_DB_DATA_DEST_MASK 0x3
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#define CORE_DB_DATA_DEST_SHIFT 0
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#define CORE_DB_DATA_AGG_CMD_MASK 0x3
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#define CORE_DB_DATA_AGG_CMD_SHIFT 2
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#define CORE_DB_DATA_BYPASS_EN_MASK 0x1
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#define CORE_DB_DATA_BYPASS_EN_SHIFT 4
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#define CORE_DB_DATA_RESERVED_MASK 0x1
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#define CORE_DB_DATA_RESERVED_SHIFT 5
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#define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
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#define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
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u8 agg_flags;
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__le16 spq_prod;
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};
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/* Enum of doorbell aggregative command selection */
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enum db_agg_cmd_sel {
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DB_AGG_CMD_NOP,
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DB_AGG_CMD_SET,
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DB_AGG_CMD_ADD,
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DB_AGG_CMD_MAX,
|
|
MAX_DB_AGG_CMD_SEL
|
|
};
|
|
|
|
/* Enum of doorbell destination */
|
|
enum db_dest {
|
|
DB_DEST_XCM,
|
|
DB_DEST_UCM,
|
|
DB_DEST_TCM,
|
|
DB_NUM_DESTINATIONS,
|
|
MAX_DB_DEST
|
|
};
|
|
|
|
/* Structure for doorbell address, in legacy mode */
|
|
struct db_legacy_addr {
|
|
__le32 addr;
|
|
#define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
|
|
#define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
|
|
#define DB_LEGACY_ADDR_DEMS_MASK 0x7
|
|
#define DB_LEGACY_ADDR_DEMS_SHIFT 2
|
|
#define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF
|
|
#define DB_LEGACY_ADDR_ICID_SHIFT 5
|
|
};
|
|
|
|
/* Igu interrupt command */
|
|
enum igu_int_cmd {
|
|
IGU_INT_ENABLE = 0,
|
|
IGU_INT_DISABLE = 1,
|
|
IGU_INT_NOP = 2,
|
|
IGU_INT_NOP2 = 3,
|
|
MAX_IGU_INT_CMD
|
|
};
|
|
|
|
/* IGU producer or consumer update command */
|
|
struct igu_prod_cons_update {
|
|
u32 sb_id_and_flags;
|
|
#define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
|
|
#define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
|
|
#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
|
|
#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24
|
|
#define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
|
|
#define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25
|
|
#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
|
|
#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
|
|
#define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
|
|
#define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28
|
|
#define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
|
|
#define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29
|
|
#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
|
|
#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31
|
|
u32 reserved1;
|
|
};
|
|
|
|
/* Igu segments access for default status block only */
|
|
enum igu_seg_access {
|
|
IGU_SEG_ACCESS_REG = 0,
|
|
IGU_SEG_ACCESS_ATTN = 1,
|
|
MAX_IGU_SEG_ACCESS
|
|
};
|
|
|
|
struct parsing_and_err_flags {
|
|
__le16 flags;
|
|
#define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
|
|
#define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
|
|
#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
|
|
#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2
|
|
#define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
|
|
#define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4
|
|
#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
|
|
#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5
|
|
#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
|
|
#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6
|
|
#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
|
|
#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7
|
|
#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
|
|
#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8
|
|
#define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
|
|
#define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9
|
|
#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
|
|
#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10
|
|
#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
|
|
#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11
|
|
#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
|
|
#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12
|
|
#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
|
|
#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13
|
|
#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
|
|
#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
|
|
#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
|
|
#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
|
|
};
|
|
|
|
/* Concrete Function ID. */
|
|
struct pxp_concrete_fid {
|
|
__le16 fid;
|
|
#define PXP_CONCRETE_FID_PFID_MASK 0xF
|
|
#define PXP_CONCRETE_FID_PFID_SHIFT 0
|
|
#define PXP_CONCRETE_FID_PORT_MASK 0x3
|
|
#define PXP_CONCRETE_FID_PORT_SHIFT 4
|
|
#define PXP_CONCRETE_FID_PATH_MASK 0x1
|
|
#define PXP_CONCRETE_FID_PATH_SHIFT 6
|
|
#define PXP_CONCRETE_FID_VFVALID_MASK 0x1
|
|
#define PXP_CONCRETE_FID_VFVALID_SHIFT 7
|
|
#define PXP_CONCRETE_FID_VFID_MASK 0xFF
|
|
#define PXP_CONCRETE_FID_VFID_SHIFT 8
|
|
};
|
|
|
|
struct pxp_pretend_concrete_fid {
|
|
__le16 fid;
|
|
#define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
|
|
#define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
|
|
#define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
|
|
#define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
|
|
#define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
|
|
#define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7
|
|
#define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
|
|
#define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8
|
|
};
|
|
|
|
union pxp_pretend_fid {
|
|
struct pxp_pretend_concrete_fid concrete_fid;
|
|
__le16 opaque_fid;
|
|
};
|
|
|
|
/* Pxp Pretend Command Register. */
|
|
struct pxp_pretend_cmd {
|
|
union pxp_pretend_fid fid;
|
|
__le16 control;
|
|
#define PXP_PRETEND_CMD_PATH_MASK 0x1
|
|
#define PXP_PRETEND_CMD_PATH_SHIFT 0
|
|
#define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
|
|
#define PXP_PRETEND_CMD_USE_PORT_SHIFT 1
|
|
#define PXP_PRETEND_CMD_PORT_MASK 0x3
|
|
#define PXP_PRETEND_CMD_PORT_SHIFT 2
|
|
#define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
|
|
#define PXP_PRETEND_CMD_RESERVED0_SHIFT 4
|
|
#define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
|
|
#define PXP_PRETEND_CMD_RESERVED1_SHIFT 8
|
|
#define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
|
|
#define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12
|
|
#define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
|
|
#define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13
|
|
#define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
|
|
#define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
|
|
#define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
|
|
#define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15
|
|
};
|
|
|
|
/* PTT Record in PXP Admin Window. */
|
|
struct pxp_ptt_entry {
|
|
__le32 offset;
|
|
#define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
|
|
#define PXP_PTT_ENTRY_OFFSET_SHIFT 0
|
|
#define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
|
|
#define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
|
|
struct pxp_pretend_cmd pretend;
|
|
};
|
|
|
|
/* RSS hash type */
|
|
enum rss_hash_type {
|
|
RSS_HASH_TYPE_DEFAULT = 0,
|
|
RSS_HASH_TYPE_IPV4 = 1,
|
|
RSS_HASH_TYPE_TCP_IPV4 = 2,
|
|
RSS_HASH_TYPE_IPV6 = 3,
|
|
RSS_HASH_TYPE_TCP_IPV6 = 4,
|
|
RSS_HASH_TYPE_UDP_IPV4 = 5,
|
|
RSS_HASH_TYPE_UDP_IPV6 = 6,
|
|
MAX_RSS_HASH_TYPE
|
|
};
|
|
|
|
/* status block structure */
|
|
struct status_block {
|
|
__le16 pi_array[PIS_PER_SB];
|
|
__le32 sb_num;
|
|
#define STATUS_BLOCK_SB_NUM_MASK 0x1FF
|
|
#define STATUS_BLOCK_SB_NUM_SHIFT 0
|
|
#define STATUS_BLOCK_ZERO_PAD_MASK 0x7F
|
|
#define STATUS_BLOCK_ZERO_PAD_SHIFT 9
|
|
#define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF
|
|
#define STATUS_BLOCK_ZERO_PAD2_SHIFT 16
|
|
__le32 prod_index;
|
|
#define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF
|
|
#define STATUS_BLOCK_PROD_INDEX_SHIFT 0
|
|
#define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF
|
|
#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
|
|
};
|
|
|
|
#endif /* __COMMON_HSI__ */
|