711 lines
20 KiB
C
711 lines
20 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/mmu_context.h>
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#include "amdgpu.h"
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#include "amdgpu_amdkfd.h"
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#include "cikd.h"
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#include "cik_sdma.h"
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#include "gfx_v7_0.h"
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#include "gca/gfx_7_2_d.h"
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#include "gca/gfx_7_2_enum.h"
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#include "gca/gfx_7_2_sh_mask.h"
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#include "oss/oss_2_0_d.h"
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#include "oss/oss_2_0_sh_mask.h"
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#include "gmc/gmc_7_1_d.h"
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#include "gmc/gmc_7_1_sh_mask.h"
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#include "cik_structs.h"
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enum hqd_dequeue_request_type {
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NO_ACTION = 0,
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DRAIN_PIPE,
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RESET_WAVES
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};
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enum {
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MAX_TRAPID = 8, /* 3 bits in the bitfield. */
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MAX_WATCH_ADDRESSES = 4
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};
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enum {
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ADDRESS_WATCH_REG_ADDR_HI = 0,
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ADDRESS_WATCH_REG_ADDR_LO,
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ADDRESS_WATCH_REG_CNTL,
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ADDRESS_WATCH_REG_MAX
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};
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/* not defined in the CI/KV reg file */
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enum {
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ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
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ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
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ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
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/* extend the mask to 26 bits to match the low address field */
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ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
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ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
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};
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static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
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mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL,
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mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL,
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mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL,
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mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL
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};
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union TCP_WATCH_CNTL_BITS {
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struct {
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uint32_t mask:24;
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uint32_t vmid:4;
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uint32_t atc:1;
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uint32_t mode:2;
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uint32_t valid:1;
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} bitfields, bits;
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uint32_t u32All;
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signed int i32All;
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float f32All;
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};
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static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
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{
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return (struct amdgpu_device *)kgd;
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}
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static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
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uint32_t queue, uint32_t vmid)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
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mutex_lock(&adev->srbm_mutex);
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WREG32(mmSRBM_GFX_CNTL, value);
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}
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static void unlock_srbm(struct kgd_dev *kgd)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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WREG32(mmSRBM_GFX_CNTL, 0);
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mutex_unlock(&adev->srbm_mutex);
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}
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static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
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uint32_t queue_id)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
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uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
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lock_srbm(kgd, mec, pipe, queue_id, 0);
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}
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static void release_queue(struct kgd_dev *kgd)
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{
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unlock_srbm(kgd);
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}
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static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
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uint32_t sh_mem_config,
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uint32_t sh_mem_ape1_base,
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uint32_t sh_mem_ape1_limit,
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uint32_t sh_mem_bases)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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lock_srbm(kgd, 0, 0, 0, vmid);
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WREG32(mmSH_MEM_CONFIG, sh_mem_config);
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WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
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WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
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WREG32(mmSH_MEM_BASES, sh_mem_bases);
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unlock_srbm(kgd);
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}
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static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
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unsigned int vmid)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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/*
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* We have to assume that there is no outstanding mapping.
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* The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
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* a mapping is in progress or because a mapping finished and the
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* SW cleared it. So the protocol is to always wait & clear.
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*/
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uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
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ATC_VMID0_PASID_MAPPING__VALID_MASK;
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WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
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while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
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cpu_relax();
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WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
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/* Mapping vmid to pasid also for IH block */
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WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
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return 0;
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}
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static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t mec;
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uint32_t pipe;
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mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
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pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
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lock_srbm(kgd, mec, pipe, 0, 0);
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WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
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CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
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unlock_srbm(kgd);
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return 0;
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}
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static inline uint32_t get_sdma_rlc_reg_offset(struct cik_sdma_rlc_registers *m)
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{
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uint32_t retval;
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retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
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m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
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pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n",
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m->sdma_engine_id, m->sdma_queue_id, retval);
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return retval;
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}
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static inline struct cik_mqd *get_mqd(void *mqd)
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{
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return (struct cik_mqd *)mqd;
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}
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static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
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{
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return (struct cik_sdma_rlc_registers *)mqd;
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}
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static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
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uint32_t queue_id, uint32_t __user *wptr,
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uint32_t wptr_shift, uint32_t wptr_mask,
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struct mm_struct *mm)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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struct cik_mqd *m;
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uint32_t *mqd_hqd;
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uint32_t reg, wptr_val, data;
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bool valid_wptr = false;
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m = get_mqd(mqd);
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acquire_queue(kgd, pipe_id, queue_id);
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/* HQD registers extend from CP_MQD_BASE_ADDR to CP_MQD_CONTROL. */
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mqd_hqd = &m->cp_mqd_base_addr_lo;
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for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
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WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
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/* Copy userspace write pointer value to register.
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* Activate doorbell logic to monitor subsequent changes.
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*/
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data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
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CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
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WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
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/* read_user_ptr may take the mm->mmap_sem.
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* release srbm_mutex to avoid circular dependency between
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* srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
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*/
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release_queue(kgd);
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valid_wptr = read_user_wptr(mm, wptr, wptr_val);
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acquire_queue(kgd, pipe_id, queue_id);
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if (valid_wptr)
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WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
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data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
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WREG32(mmCP_HQD_ACTIVE, data);
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release_queue(kgd);
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return 0;
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}
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static int kgd_hqd_dump(struct kgd_dev *kgd,
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uint32_t pipe_id, uint32_t queue_id,
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uint32_t (**dump)[2], uint32_t *n_regs)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t i = 0, reg;
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#define HQD_N_REGS (35+4)
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#define DUMP_REG(addr) do { \
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if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
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break; \
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(*dump)[i][0] = (addr) << 2; \
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(*dump)[i++][1] = RREG32(addr); \
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} while (0)
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*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
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if (*dump == NULL)
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return -ENOMEM;
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acquire_queue(kgd, pipe_id, queue_id);
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DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
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DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
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DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
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DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
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for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
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DUMP_REG(reg);
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release_queue(kgd);
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WARN_ON_ONCE(i != HQD_N_REGS);
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*n_regs = i;
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return 0;
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}
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static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
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uint32_t __user *wptr, struct mm_struct *mm)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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struct cik_sdma_rlc_registers *m;
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unsigned long end_jiffies;
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uint32_t sdma_rlc_reg_offset;
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uint32_t data;
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m = get_sdma_mqd(mqd);
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sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
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m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
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end_jiffies = msecs_to_jiffies(2000) + jiffies;
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while (true) {
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data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
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if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
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break;
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if (time_after(jiffies, end_jiffies)) {
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pr_err("SDMA RLC not idle in %s\n", __func__);
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return -ETIME;
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}
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usleep_range(500, 1000);
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}
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data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
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ENABLE, 1);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
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m->sdma_rlc_rb_rptr);
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if (read_user_wptr(mm, wptr, data))
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
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else
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
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m->sdma_rlc_rb_rptr);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
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m->sdma_rlc_virtual_addr);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
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m->sdma_rlc_rb_base_hi);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
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m->sdma_rlc_rb_rptr_addr_lo);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
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m->sdma_rlc_rb_rptr_addr_hi);
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data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
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RB_ENABLE, 1);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
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return 0;
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}
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static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
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uint32_t engine_id, uint32_t queue_id,
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uint32_t (**dump)[2], uint32_t *n_regs)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
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queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
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uint32_t i = 0, reg;
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#undef HQD_N_REGS
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#define HQD_N_REGS (19+4)
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*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
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if (*dump == NULL)
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return -ENOMEM;
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for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
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DUMP_REG(sdma_offset + reg);
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for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
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reg++)
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DUMP_REG(sdma_offset + reg);
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WARN_ON_ONCE(i != HQD_N_REGS);
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*n_regs = i;
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return 0;
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}
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static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
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uint32_t pipe_id, uint32_t queue_id)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t act;
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bool retval = false;
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uint32_t low, high;
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acquire_queue(kgd, pipe_id, queue_id);
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act = RREG32(mmCP_HQD_ACTIVE);
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if (act) {
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low = lower_32_bits(queue_address >> 8);
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high = upper_32_bits(queue_address >> 8);
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if (low == RREG32(mmCP_HQD_PQ_BASE) &&
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high == RREG32(mmCP_HQD_PQ_BASE_HI))
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retval = true;
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}
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release_queue(kgd);
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return retval;
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}
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static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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struct cik_sdma_rlc_registers *m;
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uint32_t sdma_rlc_reg_offset;
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uint32_t sdma_rlc_rb_cntl;
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m = get_sdma_mqd(mqd);
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sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
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sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
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if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
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return true;
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return false;
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}
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static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
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enum kfd_preempt_type reset_type,
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unsigned int utimeout, uint32_t pipe_id,
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uint32_t queue_id)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t temp;
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enum hqd_dequeue_request_type type;
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unsigned long flags, end_jiffies;
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int retry;
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if (adev->in_gpu_reset)
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return -EIO;
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acquire_queue(kgd, pipe_id, queue_id);
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WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
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|
|
switch (reset_type) {
|
|
case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
|
|
type = DRAIN_PIPE;
|
|
break;
|
|
case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
|
|
type = RESET_WAVES;
|
|
break;
|
|
default:
|
|
type = DRAIN_PIPE;
|
|
break;
|
|
}
|
|
|
|
/* Workaround: If IQ timer is active and the wait time is close to or
|
|
* equal to 0, dequeueing is not safe. Wait until either the wait time
|
|
* is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
|
|
* cleared before continuing. Also, ensure wait times are set to at
|
|
* least 0x3.
|
|
*/
|
|
local_irq_save(flags);
|
|
preempt_disable();
|
|
retry = 5000; /* wait for 500 usecs at maximum */
|
|
while (true) {
|
|
temp = RREG32(mmCP_HQD_IQ_TIMER);
|
|
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
|
|
pr_debug("HW is processing IQ\n");
|
|
goto loop;
|
|
}
|
|
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
|
|
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
|
|
== 3) /* SEM-rearm is safe */
|
|
break;
|
|
/* Wait time 3 is safe for CP, but our MMIO read/write
|
|
* time is close to 1 microsecond, so check for 10 to
|
|
* leave more buffer room
|
|
*/
|
|
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
|
|
>= 10)
|
|
break;
|
|
pr_debug("IQ timer is active\n");
|
|
} else
|
|
break;
|
|
loop:
|
|
if (!retry) {
|
|
pr_err("CP HQD IQ timer status time out\n");
|
|
break;
|
|
}
|
|
ndelay(100);
|
|
--retry;
|
|
}
|
|
retry = 1000;
|
|
while (true) {
|
|
temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
|
|
if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
|
|
break;
|
|
pr_debug("Dequeue request is pending\n");
|
|
|
|
if (!retry) {
|
|
pr_err("CP HQD dequeue request time out\n");
|
|
break;
|
|
}
|
|
ndelay(100);
|
|
--retry;
|
|
}
|
|
local_irq_restore(flags);
|
|
preempt_enable();
|
|
|
|
WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
|
|
|
|
end_jiffies = (utimeout * HZ / 1000) + jiffies;
|
|
while (true) {
|
|
temp = RREG32(mmCP_HQD_ACTIVE);
|
|
if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
|
|
break;
|
|
if (time_after(jiffies, end_jiffies)) {
|
|
pr_err("cp queue preemption time out\n");
|
|
release_queue(kgd);
|
|
return -ETIME;
|
|
}
|
|
usleep_range(500, 1000);
|
|
}
|
|
|
|
release_queue(kgd);
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
|
|
unsigned int utimeout)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
struct cik_sdma_rlc_registers *m;
|
|
uint32_t sdma_rlc_reg_offset;
|
|
uint32_t temp;
|
|
unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
|
|
|
|
m = get_sdma_mqd(mqd);
|
|
sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
|
|
|
|
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
|
|
temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
|
|
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
|
|
|
|
while (true) {
|
|
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
|
|
if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
|
|
break;
|
|
if (time_after(jiffies, end_jiffies)) {
|
|
pr_err("SDMA RLC not idle in %s\n", __func__);
|
|
return -ETIME;
|
|
}
|
|
usleep_range(500, 1000);
|
|
}
|
|
|
|
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
|
|
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
|
|
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
|
|
SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
|
|
|
|
m->sdma_rlc_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_address_watch_disable(struct kgd_dev *kgd)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
union TCP_WATCH_CNTL_BITS cntl;
|
|
unsigned int i;
|
|
|
|
cntl.u32All = 0;
|
|
|
|
cntl.bitfields.valid = 0;
|
|
cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
|
|
cntl.bitfields.atc = 1;
|
|
|
|
/* Turning off this address until we set all the registers */
|
|
for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
|
|
WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_CNTL], cntl.u32All);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_address_watch_execute(struct kgd_dev *kgd,
|
|
unsigned int watch_point_id,
|
|
uint32_t cntl_val,
|
|
uint32_t addr_hi,
|
|
uint32_t addr_lo)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
union TCP_WATCH_CNTL_BITS cntl;
|
|
|
|
cntl.u32All = cntl_val;
|
|
|
|
/* Turning off this watch point until we set all the registers */
|
|
cntl.bitfields.valid = 0;
|
|
WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_CNTL], cntl.u32All);
|
|
|
|
WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_ADDR_HI], addr_hi);
|
|
|
|
WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_ADDR_LO], addr_lo);
|
|
|
|
/* Enable the watch point */
|
|
cntl.bitfields.valid = 1;
|
|
|
|
WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_CNTL], cntl.u32All);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_wave_control_execute(struct kgd_dev *kgd,
|
|
uint32_t gfx_index_val,
|
|
uint32_t sq_cmd)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
uint32_t data;
|
|
|
|
mutex_lock(&adev->grbm_idx_mutex);
|
|
|
|
WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
|
|
WREG32(mmSQ_CMD, sq_cmd);
|
|
|
|
/* Restore the GRBM_GFX_INDEX register */
|
|
|
|
data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK |
|
|
GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
|
|
GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
|
|
|
|
WREG32(mmGRBM_GFX_INDEX, data);
|
|
|
|
mutex_unlock(&adev->grbm_idx_mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
|
|
unsigned int watch_point_id,
|
|
unsigned int reg_offset)
|
|
{
|
|
return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
|
|
}
|
|
|
|
static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
|
|
uint8_t vmid, uint16_t *p_pasid)
|
|
{
|
|
uint32_t value;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
|
|
|
|
value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
|
|
*p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
|
|
|
|
return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
|
|
}
|
|
|
|
static void set_scratch_backing_va(struct kgd_dev *kgd,
|
|
uint64_t va, uint32_t vmid)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
|
|
|
|
lock_srbm(kgd, 0, 0, 0, vmid);
|
|
WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
|
|
unlock_srbm(kgd);
|
|
}
|
|
|
|
static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
|
|
uint64_t page_table_base)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
|
|
if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
|
|
pr_err("trying to set page table base for wrong VMID\n");
|
|
return;
|
|
}
|
|
WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,
|
|
lower_32_bits(page_table_base));
|
|
}
|
|
|
|
/**
|
|
* read_vmid_from_vmfault_reg - read vmid from register
|
|
*
|
|
* adev: amdgpu_device pointer
|
|
* @vmid: vmid pointer
|
|
* read vmid from register (CIK).
|
|
*/
|
|
static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
|
|
uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
|
|
|
|
return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
|
|
}
|
|
|
|
const struct kfd2kgd_calls gfx_v7_kfd2kgd = {
|
|
.program_sh_mem_settings = kgd_program_sh_mem_settings,
|
|
.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
|
|
.init_interrupts = kgd_init_interrupts,
|
|
.hqd_load = kgd_hqd_load,
|
|
.hqd_sdma_load = kgd_hqd_sdma_load,
|
|
.hqd_dump = kgd_hqd_dump,
|
|
.hqd_sdma_dump = kgd_hqd_sdma_dump,
|
|
.hqd_is_occupied = kgd_hqd_is_occupied,
|
|
.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
|
|
.hqd_destroy = kgd_hqd_destroy,
|
|
.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
|
|
.address_watch_disable = kgd_address_watch_disable,
|
|
.address_watch_execute = kgd_address_watch_execute,
|
|
.wave_control_execute = kgd_wave_control_execute,
|
|
.address_watch_get_offset = kgd_address_watch_get_offset,
|
|
.get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,
|
|
.set_scratch_backing_va = set_scratch_backing_va,
|
|
.set_vm_context_page_table_base = set_vm_context_page_table_base,
|
|
.read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
|
|
};
|