492 lines
16 KiB
C
492 lines
16 KiB
C
/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2014 Endless Mobile
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Written by:
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* Jasper St. Pierre <jstpierre@mecheye.net>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/bitfield.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_flip_work.h>
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#include <drm/drm_crtc_helper.h>
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#include "meson_crtc.h"
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#include "meson_plane.h"
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#include "meson_venc.h"
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#include "meson_vpp.h"
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#include "meson_viu.h"
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#include "meson_canvas.h"
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#include "meson_registers.h"
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/* CRTC definition */
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struct meson_crtc {
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struct drm_crtc base;
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struct drm_pending_vblank_event *event;
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struct meson_drm *priv;
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bool enabled;
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};
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#define to_meson_crtc(x) container_of(x, struct meson_crtc, base)
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/* CRTC */
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static int meson_crtc_enable_vblank(struct drm_crtc *crtc)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
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struct meson_drm *priv = meson_crtc->priv;
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meson_venc_enable_vsync(priv);
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return 0;
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}
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static void meson_crtc_disable_vblank(struct drm_crtc *crtc)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
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struct meson_drm *priv = meson_crtc->priv;
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meson_venc_disable_vsync(priv);
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}
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static const struct drm_crtc_funcs meson_crtc_funcs = {
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.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
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.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
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.destroy = drm_crtc_cleanup,
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.page_flip = drm_atomic_helper_page_flip,
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.reset = drm_atomic_helper_crtc_reset,
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.set_config = drm_atomic_helper_set_config,
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.enable_vblank = meson_crtc_enable_vblank,
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.disable_vblank = meson_crtc_disable_vblank,
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};
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static void meson_crtc_enable(struct drm_crtc *crtc)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
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struct drm_crtc_state *crtc_state = crtc->state;
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struct meson_drm *priv = meson_crtc->priv;
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DRM_DEBUG_DRIVER("\n");
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if (!crtc_state) {
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DRM_ERROR("Invalid crtc_state\n");
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return;
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}
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/* Enable VPP Postblend */
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writel(crtc_state->mode.hdisplay,
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priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
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/* VD1 Preblend vertical start/end */
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writel(FIELD_PREP(GENMASK(11, 0), 2303),
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priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));
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writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
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priv->io_base + _REG(VPP_MISC));
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drm_crtc_vblank_on(crtc);
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meson_crtc->enabled = true;
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}
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static void meson_crtc_atomic_enable(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
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struct meson_drm *priv = meson_crtc->priv;
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DRM_DEBUG_DRIVER("\n");
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if (!meson_crtc->enabled)
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meson_crtc_enable(crtc);
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priv->viu.osd1_enabled = true;
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}
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static void meson_crtc_atomic_disable(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
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struct meson_drm *priv = meson_crtc->priv;
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DRM_DEBUG_DRIVER("\n");
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drm_crtc_vblank_off(crtc);
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priv->viu.osd1_enabled = false;
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priv->viu.osd1_commit = false;
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priv->viu.vd1_enabled = false;
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priv->viu.vd1_commit = false;
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/* Disable VPP Postblend */
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writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_VD1_POSTBLEND |
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VPP_VD1_PREBLEND | VPP_POSTBLEND_ENABLE, 0,
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priv->io_base + _REG(VPP_MISC));
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if (crtc->state->event && !crtc->state->active) {
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spin_lock_irq(&crtc->dev->event_lock);
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drm_crtc_send_vblank_event(crtc, crtc->state->event);
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spin_unlock_irq(&crtc->dev->event_lock);
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crtc->state->event = NULL;
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}
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meson_crtc->enabled = false;
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}
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static void meson_crtc_atomic_begin(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
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unsigned long flags;
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if (crtc->state->enable && !meson_crtc->enabled)
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meson_crtc_enable(crtc);
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if (crtc->state->event) {
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WARN_ON(drm_crtc_vblank_get(crtc) != 0);
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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meson_crtc->event = crtc->state->event;
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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crtc->state->event = NULL;
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}
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}
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static void meson_crtc_atomic_flush(struct drm_crtc *crtc,
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struct drm_crtc_state *old_crtc_state)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
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struct meson_drm *priv = meson_crtc->priv;
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priv->viu.osd1_commit = true;
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priv->viu.vd1_commit = true;
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}
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static const struct drm_crtc_helper_funcs meson_crtc_helper_funcs = {
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.atomic_begin = meson_crtc_atomic_begin,
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.atomic_flush = meson_crtc_atomic_flush,
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.atomic_enable = meson_crtc_atomic_enable,
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.atomic_disable = meson_crtc_atomic_disable,
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};
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void meson_crtc_irq(struct meson_drm *priv)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(priv->crtc);
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unsigned long flags;
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/* Update the OSD registers */
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if (priv->viu.osd1_enabled && priv->viu.osd1_commit) {
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writel_relaxed(priv->viu.osd1_ctrl_stat,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
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writel_relaxed(priv->viu.osd1_blk0_cfg[0],
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priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
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writel_relaxed(priv->viu.osd1_blk0_cfg[1],
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priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1));
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writel_relaxed(priv->viu.osd1_blk0_cfg[2],
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priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2));
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writel_relaxed(priv->viu.osd1_blk0_cfg[3],
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priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3));
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writel_relaxed(priv->viu.osd1_blk0_cfg[4],
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priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4));
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writel_relaxed(priv->viu.osd_sc_ctrl0,
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priv->io_base + _REG(VPP_OSD_SC_CTRL0));
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writel_relaxed(priv->viu.osd_sc_i_wh_m1,
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priv->io_base + _REG(VPP_OSD_SCI_WH_M1));
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writel_relaxed(priv->viu.osd_sc_o_h_start_end,
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priv->io_base + _REG(VPP_OSD_SCO_H_START_END));
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writel_relaxed(priv->viu.osd_sc_o_v_start_end,
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priv->io_base + _REG(VPP_OSD_SCO_V_START_END));
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writel_relaxed(priv->viu.osd_sc_v_ini_phase,
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priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));
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writel_relaxed(priv->viu.osd_sc_v_phase_step,
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priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));
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writel_relaxed(priv->viu.osd_sc_h_ini_phase,
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priv->io_base + _REG(VPP_OSD_HSC_INI_PHASE));
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writel_relaxed(priv->viu.osd_sc_h_phase_step,
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priv->io_base + _REG(VPP_OSD_HSC_PHASE_STEP));
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writel_relaxed(priv->viu.osd_sc_h_ctrl0,
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priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
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writel_relaxed(priv->viu.osd_sc_v_ctrl0,
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priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
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if (priv->canvas)
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meson_canvas_config(priv->canvas, priv->canvas_id_osd1,
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priv->viu.osd1_addr, priv->viu.osd1_stride,
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priv->viu.osd1_height, MESON_CANVAS_WRAP_NONE,
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MESON_CANVAS_BLKMODE_LINEAR, 0);
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else
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meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
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priv->viu.osd1_addr, priv->viu.osd1_stride,
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priv->viu.osd1_height, MESON_CANVAS_WRAP_NONE,
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MESON_CANVAS_BLKMODE_LINEAR, 0);
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/* Enable OSD1 */
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writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
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priv->io_base + _REG(VPP_MISC));
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priv->viu.osd1_commit = false;
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}
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/* Update the VD1 registers */
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if (priv->viu.vd1_enabled && priv->viu.vd1_commit) {
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switch (priv->viu.vd1_planes) {
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case 3:
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if (priv->canvas)
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meson_canvas_config(priv->canvas,
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priv->canvas_id_vd1_2,
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priv->viu.vd1_addr2,
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priv->viu.vd1_stride2,
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priv->viu.vd1_height2,
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MESON_CANVAS_WRAP_NONE,
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MESON_CANVAS_BLKMODE_LINEAR,
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MESON_CANVAS_ENDIAN_SWAP64);
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else
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meson_canvas_setup(priv, MESON_CANVAS_ID_VD1_2,
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priv->viu.vd1_addr2,
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priv->viu.vd1_stride2,
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priv->viu.vd1_height2,
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MESON_CANVAS_WRAP_NONE,
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MESON_CANVAS_BLKMODE_LINEAR,
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MESON_CANVAS_ENDIAN_SWAP64);
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/* fallthrough */
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case 2:
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if (priv->canvas)
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meson_canvas_config(priv->canvas,
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priv->canvas_id_vd1_1,
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priv->viu.vd1_addr1,
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priv->viu.vd1_stride1,
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priv->viu.vd1_height1,
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MESON_CANVAS_WRAP_NONE,
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MESON_CANVAS_BLKMODE_LINEAR,
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MESON_CANVAS_ENDIAN_SWAP64);
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else
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meson_canvas_setup(priv, MESON_CANVAS_ID_VD1_1,
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priv->viu.vd1_addr2,
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priv->viu.vd1_stride2,
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priv->viu.vd1_height2,
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MESON_CANVAS_WRAP_NONE,
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MESON_CANVAS_BLKMODE_LINEAR,
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MESON_CANVAS_ENDIAN_SWAP64);
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/* fallthrough */
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case 1:
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if (priv->canvas)
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meson_canvas_config(priv->canvas,
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priv->canvas_id_vd1_0,
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priv->viu.vd1_addr0,
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priv->viu.vd1_stride0,
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priv->viu.vd1_height0,
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MESON_CANVAS_WRAP_NONE,
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MESON_CANVAS_BLKMODE_LINEAR,
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MESON_CANVAS_ENDIAN_SWAP64);
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else
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meson_canvas_setup(priv, MESON_CANVAS_ID_VD1_0,
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priv->viu.vd1_addr2,
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priv->viu.vd1_stride2,
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priv->viu.vd1_height2,
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MESON_CANVAS_WRAP_NONE,
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MESON_CANVAS_BLKMODE_LINEAR,
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MESON_CANVAS_ENDIAN_SWAP64);
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};
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writel_relaxed(priv->viu.vd1_if0_gen_reg,
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priv->io_base + _REG(VD1_IF0_GEN_REG));
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writel_relaxed(priv->viu.vd1_if0_gen_reg,
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priv->io_base + _REG(VD2_IF0_GEN_REG));
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writel_relaxed(priv->viu.vd1_if0_gen_reg2,
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priv->io_base + _REG(VD1_IF0_GEN_REG2));
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writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
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priv->io_base + _REG(VIU_VD1_FMT_CTRL));
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writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
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priv->io_base + _REG(VIU_VD2_FMT_CTRL));
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writel_relaxed(priv->viu.viu_vd1_fmt_w,
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priv->io_base + _REG(VIU_VD1_FMT_W));
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writel_relaxed(priv->viu.viu_vd1_fmt_w,
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priv->io_base + _REG(VIU_VD2_FMT_W));
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writel_relaxed(priv->viu.vd1_if0_canvas0,
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priv->io_base + _REG(VD1_IF0_CANVAS0));
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writel_relaxed(priv->viu.vd1_if0_canvas0,
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priv->io_base + _REG(VD1_IF0_CANVAS1));
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writel_relaxed(priv->viu.vd1_if0_canvas0,
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priv->io_base + _REG(VD2_IF0_CANVAS0));
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writel_relaxed(priv->viu.vd1_if0_canvas0,
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priv->io_base + _REG(VD2_IF0_CANVAS1));
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writel_relaxed(priv->viu.vd1_if0_luma_x0,
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priv->io_base + _REG(VD1_IF0_LUMA_X0));
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writel_relaxed(priv->viu.vd1_if0_luma_x0,
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priv->io_base + _REG(VD1_IF0_LUMA_X1));
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writel_relaxed(priv->viu.vd1_if0_luma_x0,
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priv->io_base + _REG(VD2_IF0_LUMA_X0));
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writel_relaxed(priv->viu.vd1_if0_luma_x0,
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priv->io_base + _REG(VD2_IF0_LUMA_X1));
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writel_relaxed(priv->viu.vd1_if0_luma_y0,
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priv->io_base + _REG(VD1_IF0_LUMA_Y0));
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writel_relaxed(priv->viu.vd1_if0_luma_y0,
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priv->io_base + _REG(VD1_IF0_LUMA_Y1));
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writel_relaxed(priv->viu.vd1_if0_luma_y0,
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priv->io_base + _REG(VD2_IF0_LUMA_Y0));
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writel_relaxed(priv->viu.vd1_if0_luma_y0,
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priv->io_base + _REG(VD2_IF0_LUMA_Y1));
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writel_relaxed(priv->viu.vd1_if0_chroma_x0,
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priv->io_base + _REG(VD1_IF0_CHROMA_X0));
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writel_relaxed(priv->viu.vd1_if0_chroma_x0,
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priv->io_base + _REG(VD1_IF0_CHROMA_X1));
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writel_relaxed(priv->viu.vd1_if0_chroma_x0,
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priv->io_base + _REG(VD2_IF0_CHROMA_X0));
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writel_relaxed(priv->viu.vd1_if0_chroma_x0,
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priv->io_base + _REG(VD2_IF0_CHROMA_X1));
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writel_relaxed(priv->viu.vd1_if0_chroma_y0,
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priv->io_base + _REG(VD1_IF0_CHROMA_Y0));
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writel_relaxed(priv->viu.vd1_if0_chroma_y0,
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priv->io_base + _REG(VD1_IF0_CHROMA_Y1));
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writel_relaxed(priv->viu.vd1_if0_chroma_y0,
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priv->io_base + _REG(VD2_IF0_CHROMA_Y0));
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writel_relaxed(priv->viu.vd1_if0_chroma_y0,
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priv->io_base + _REG(VD2_IF0_CHROMA_Y1));
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writel_relaxed(priv->viu.vd1_if0_repeat_loop,
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priv->io_base + _REG(VD1_IF0_RPT_LOOP));
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writel_relaxed(priv->viu.vd1_if0_repeat_loop,
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priv->io_base + _REG(VD2_IF0_RPT_LOOP));
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writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
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priv->io_base + _REG(VD1_IF0_LUMA0_RPT_PAT));
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writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
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priv->io_base + _REG(VD2_IF0_LUMA0_RPT_PAT));
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writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
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priv->io_base + _REG(VD1_IF0_LUMA1_RPT_PAT));
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writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
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priv->io_base + _REG(VD2_IF0_LUMA1_RPT_PAT));
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writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
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priv->io_base + _REG(VD1_IF0_CHROMA0_RPT_PAT));
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writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
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priv->io_base + _REG(VD2_IF0_CHROMA0_RPT_PAT));
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writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
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priv->io_base + _REG(VD1_IF0_CHROMA1_RPT_PAT));
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writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
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priv->io_base + _REG(VD2_IF0_CHROMA1_RPT_PAT));
|
|
writel_relaxed(0, priv->io_base + _REG(VD1_IF0_LUMA_PSEL));
|
|
writel_relaxed(0, priv->io_base + _REG(VD1_IF0_CHROMA_PSEL));
|
|
writel_relaxed(0, priv->io_base + _REG(VD2_IF0_LUMA_PSEL));
|
|
writel_relaxed(0, priv->io_base + _REG(VD2_IF0_CHROMA_PSEL));
|
|
writel_relaxed(priv->viu.vd1_range_map_y,
|
|
priv->io_base + _REG(VD1_IF0_RANGE_MAP_Y));
|
|
writel_relaxed(priv->viu.vd1_range_map_cb,
|
|
priv->io_base + _REG(VD1_IF0_RANGE_MAP_CB));
|
|
writel_relaxed(priv->viu.vd1_range_map_cr,
|
|
priv->io_base + _REG(VD1_IF0_RANGE_MAP_CR));
|
|
writel_relaxed(0x78404,
|
|
priv->io_base + _REG(VPP_SC_MISC));
|
|
writel_relaxed(priv->viu.vpp_pic_in_height,
|
|
priv->io_base + _REG(VPP_PIC_IN_HEIGHT));
|
|
writel_relaxed(priv->viu.vpp_postblend_vd1_h_start_end,
|
|
priv->io_base + _REG(VPP_POSTBLEND_VD1_H_START_END));
|
|
writel_relaxed(priv->viu.vpp_blend_vd2_h_start_end,
|
|
priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
|
|
writel_relaxed(priv->viu.vpp_postblend_vd1_v_start_end,
|
|
priv->io_base + _REG(VPP_POSTBLEND_VD1_V_START_END));
|
|
writel_relaxed(priv->viu.vpp_blend_vd2_v_start_end,
|
|
priv->io_base + _REG(VPP_BLEND_VD2_V_START_END));
|
|
writel_relaxed(priv->viu.vpp_hsc_region12_startp,
|
|
priv->io_base + _REG(VPP_HSC_REGION12_STARTP));
|
|
writel_relaxed(priv->viu.vpp_hsc_region34_startp,
|
|
priv->io_base + _REG(VPP_HSC_REGION34_STARTP));
|
|
writel_relaxed(priv->viu.vpp_hsc_region4_endp,
|
|
priv->io_base + _REG(VPP_HSC_REGION4_ENDP));
|
|
writel_relaxed(priv->viu.vpp_hsc_start_phase_step,
|
|
priv->io_base + _REG(VPP_HSC_START_PHASE_STEP));
|
|
writel_relaxed(priv->viu.vpp_hsc_region1_phase_slope,
|
|
priv->io_base + _REG(VPP_HSC_REGION1_PHASE_SLOPE));
|
|
writel_relaxed(priv->viu.vpp_hsc_region3_phase_slope,
|
|
priv->io_base + _REG(VPP_HSC_REGION3_PHASE_SLOPE));
|
|
writel_relaxed(priv->viu.vpp_line_in_length,
|
|
priv->io_base + _REG(VPP_LINE_IN_LENGTH));
|
|
writel_relaxed(priv->viu.vpp_preblend_h_size,
|
|
priv->io_base + _REG(VPP_PREBLEND_H_SIZE));
|
|
writel_relaxed(priv->viu.vpp_vsc_region12_startp,
|
|
priv->io_base + _REG(VPP_VSC_REGION12_STARTP));
|
|
writel_relaxed(priv->viu.vpp_vsc_region34_startp,
|
|
priv->io_base + _REG(VPP_VSC_REGION34_STARTP));
|
|
writel_relaxed(priv->viu.vpp_vsc_region4_endp,
|
|
priv->io_base + _REG(VPP_VSC_REGION4_ENDP));
|
|
writel_relaxed(priv->viu.vpp_vsc_start_phase_step,
|
|
priv->io_base + _REG(VPP_VSC_START_PHASE_STEP));
|
|
writel_relaxed(priv->viu.vpp_vsc_ini_phase,
|
|
priv->io_base + _REG(VPP_VSC_INI_PHASE));
|
|
writel_relaxed(priv->viu.vpp_vsc_phase_ctrl,
|
|
priv->io_base + _REG(VPP_VSC_PHASE_CTRL));
|
|
writel_relaxed(priv->viu.vpp_hsc_phase_ctrl,
|
|
priv->io_base + _REG(VPP_HSC_PHASE_CTRL));
|
|
writel_relaxed(0x42, priv->io_base + _REG(VPP_SCALE_COEF_IDX));
|
|
|
|
/* Enable VD1 */
|
|
writel_bits_relaxed(VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND |
|
|
VPP_COLOR_MNG_ENABLE,
|
|
VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND |
|
|
VPP_COLOR_MNG_ENABLE,
|
|
priv->io_base + _REG(VPP_MISC));
|
|
|
|
priv->viu.vd1_commit = false;
|
|
}
|
|
|
|
drm_crtc_handle_vblank(priv->crtc);
|
|
|
|
spin_lock_irqsave(&priv->drm->event_lock, flags);
|
|
if (meson_crtc->event) {
|
|
drm_crtc_send_vblank_event(priv->crtc, meson_crtc->event);
|
|
drm_crtc_vblank_put(priv->crtc);
|
|
meson_crtc->event = NULL;
|
|
}
|
|
spin_unlock_irqrestore(&priv->drm->event_lock, flags);
|
|
}
|
|
|
|
int meson_crtc_create(struct meson_drm *priv)
|
|
{
|
|
struct meson_crtc *meson_crtc;
|
|
struct drm_crtc *crtc;
|
|
int ret;
|
|
|
|
meson_crtc = devm_kzalloc(priv->drm->dev, sizeof(*meson_crtc),
|
|
GFP_KERNEL);
|
|
if (!meson_crtc)
|
|
return -ENOMEM;
|
|
|
|
meson_crtc->priv = priv;
|
|
crtc = &meson_crtc->base;
|
|
ret = drm_crtc_init_with_planes(priv->drm, crtc,
|
|
priv->primary_plane, NULL,
|
|
&meson_crtc_funcs, "meson_crtc");
|
|
if (ret) {
|
|
dev_err(priv->drm->dev, "Failed to init CRTC\n");
|
|
return ret;
|
|
}
|
|
|
|
drm_crtc_helper_add(crtc, &meson_crtc_helper_funcs);
|
|
|
|
priv->crtc = crtc;
|
|
|
|
return 0;
|
|
}
|