447 lines
14 KiB
C
447 lines
14 KiB
C
/*
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* Copyright (C) 2014 Traphandler
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* Copyright (C) 2014 Free Electrons
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* Copyright (C) 2014 Atmel
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*
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* Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef DRM_ATMEL_HLCDC_H
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#define DRM_ATMEL_HLCDC_H
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#include <linux/clk.h>
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#include <linux/dmapool.h>
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#include <linux/irqdomain.h>
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#include <linux/mfd/atmel-hlcdc.h>
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#include <linux/pwm.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_gem_framebuffer_helper.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drmP.h>
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#define ATMEL_HLCDC_LAYER_CHER 0x0
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#define ATMEL_HLCDC_LAYER_CHDR 0x4
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#define ATMEL_HLCDC_LAYER_CHSR 0x8
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#define ATMEL_HLCDC_LAYER_EN BIT(0)
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#define ATMEL_HLCDC_LAYER_UPDATE BIT(1)
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#define ATMEL_HLCDC_LAYER_A2Q BIT(2)
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#define ATMEL_HLCDC_LAYER_RST BIT(8)
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#define ATMEL_HLCDC_LAYER_IER 0xc
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#define ATMEL_HLCDC_LAYER_IDR 0x10
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#define ATMEL_HLCDC_LAYER_IMR 0x14
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#define ATMEL_HLCDC_LAYER_ISR 0x18
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#define ATMEL_HLCDC_LAYER_DFETCH BIT(0)
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#define ATMEL_HLCDC_LAYER_LFETCH BIT(1)
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#define ATMEL_HLCDC_LAYER_DMA_IRQ(p) BIT(2 + (8 * (p)))
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#define ATMEL_HLCDC_LAYER_DSCR_IRQ(p) BIT(3 + (8 * (p)))
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#define ATMEL_HLCDC_LAYER_ADD_IRQ(p) BIT(4 + (8 * (p)))
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#define ATMEL_HLCDC_LAYER_DONE_IRQ(p) BIT(5 + (8 * (p)))
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#define ATMEL_HLCDC_LAYER_OVR_IRQ(p) BIT(6 + (8 * (p)))
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#define ATMEL_HLCDC_LAYER_PLANE_HEAD(p) (((p) * 0x10) + 0x1c)
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#define ATMEL_HLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x10) + 0x20)
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#define ATMEL_HLCDC_LAYER_PLANE_CTRL(p) (((p) * 0x10) + 0x24)
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#define ATMEL_HLCDC_LAYER_PLANE_NEXT(p) (((p) * 0x10) + 0x28)
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#define ATMEL_HLCDC_LAYER_DMA_CFG 0
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#define ATMEL_HLCDC_LAYER_DMA_SIF BIT(0)
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#define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK GENMASK(5, 4)
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#define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE (0 << 4)
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#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4 (1 << 4)
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#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8 (2 << 4)
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#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 (3 << 4)
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#define ATMEL_HLCDC_LAYER_DMA_DLBO BIT(8)
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#define ATMEL_HLCDC_LAYER_DMA_ROTDIS BIT(12)
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#define ATMEL_HLCDC_LAYER_DMA_LOCKDIS BIT(13)
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#define ATMEL_HLCDC_LAYER_FORMAT_CFG 1
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#define ATMEL_HLCDC_LAYER_RGB (0 << 0)
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#define ATMEL_HLCDC_LAYER_CLUT (1 << 0)
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#define ATMEL_HLCDC_LAYER_YUV (2 << 0)
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#define ATMEL_HLCDC_RGB_MODE(m) \
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(ATMEL_HLCDC_LAYER_RGB | (((m) & 0xf) << 4))
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#define ATMEL_HLCDC_CLUT_MODE(m) \
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(ATMEL_HLCDC_LAYER_CLUT | (((m) & 0x3) << 8))
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#define ATMEL_HLCDC_YUV_MODE(m) \
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(ATMEL_HLCDC_LAYER_YUV | (((m) & 0xf) << 12))
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#define ATMEL_HLCDC_YUV422ROT BIT(16)
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#define ATMEL_HLCDC_YUV422SWP BIT(17)
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#define ATMEL_HLCDC_DSCALEOPT BIT(20)
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#define ATMEL_HLCDC_C1_MODE ATMEL_HLCDC_CLUT_MODE(0)
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#define ATMEL_HLCDC_C2_MODE ATMEL_HLCDC_CLUT_MODE(1)
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#define ATMEL_HLCDC_C4_MODE ATMEL_HLCDC_CLUT_MODE(2)
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#define ATMEL_HLCDC_C8_MODE ATMEL_HLCDC_CLUT_MODE(3)
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#define ATMEL_HLCDC_XRGB4444_MODE ATMEL_HLCDC_RGB_MODE(0)
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#define ATMEL_HLCDC_ARGB4444_MODE ATMEL_HLCDC_RGB_MODE(1)
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#define ATMEL_HLCDC_RGBA4444_MODE ATMEL_HLCDC_RGB_MODE(2)
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#define ATMEL_HLCDC_RGB565_MODE ATMEL_HLCDC_RGB_MODE(3)
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#define ATMEL_HLCDC_ARGB1555_MODE ATMEL_HLCDC_RGB_MODE(4)
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#define ATMEL_HLCDC_XRGB8888_MODE ATMEL_HLCDC_RGB_MODE(9)
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#define ATMEL_HLCDC_RGB888_MODE ATMEL_HLCDC_RGB_MODE(10)
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#define ATMEL_HLCDC_ARGB8888_MODE ATMEL_HLCDC_RGB_MODE(12)
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#define ATMEL_HLCDC_RGBA8888_MODE ATMEL_HLCDC_RGB_MODE(13)
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#define ATMEL_HLCDC_AYUV_MODE ATMEL_HLCDC_YUV_MODE(0)
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#define ATMEL_HLCDC_YUYV_MODE ATMEL_HLCDC_YUV_MODE(1)
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#define ATMEL_HLCDC_UYVY_MODE ATMEL_HLCDC_YUV_MODE(2)
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#define ATMEL_HLCDC_YVYU_MODE ATMEL_HLCDC_YUV_MODE(3)
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#define ATMEL_HLCDC_VYUY_MODE ATMEL_HLCDC_YUV_MODE(4)
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#define ATMEL_HLCDC_NV61_MODE ATMEL_HLCDC_YUV_MODE(5)
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#define ATMEL_HLCDC_YUV422_MODE ATMEL_HLCDC_YUV_MODE(6)
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#define ATMEL_HLCDC_NV21_MODE ATMEL_HLCDC_YUV_MODE(7)
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#define ATMEL_HLCDC_YUV420_MODE ATMEL_HLCDC_YUV_MODE(8)
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#define ATMEL_HLCDC_LAYER_POS(x, y) ((x) | ((y) << 16))
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#define ATMEL_HLCDC_LAYER_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
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#define ATMEL_HLCDC_LAYER_CRKEY BIT(0)
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#define ATMEL_HLCDC_LAYER_INV BIT(1)
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#define ATMEL_HLCDC_LAYER_ITER2BL BIT(2)
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#define ATMEL_HLCDC_LAYER_ITER BIT(3)
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#define ATMEL_HLCDC_LAYER_REVALPHA BIT(4)
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#define ATMEL_HLCDC_LAYER_GAEN BIT(5)
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#define ATMEL_HLCDC_LAYER_LAEN BIT(6)
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#define ATMEL_HLCDC_LAYER_OVR BIT(7)
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#define ATMEL_HLCDC_LAYER_DMA BIT(8)
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#define ATMEL_HLCDC_LAYER_REP BIT(9)
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#define ATMEL_HLCDC_LAYER_DSTKEY BIT(10)
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#define ATMEL_HLCDC_LAYER_DISCEN BIT(11)
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#define ATMEL_HLCDC_LAYER_GA_SHIFT 16
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#define ATMEL_HLCDC_LAYER_GA_MASK \
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GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT)
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#define ATMEL_HLCDC_LAYER_GA(x) \
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((x) << ATMEL_HLCDC_LAYER_GA_SHIFT)
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#define ATMEL_HLCDC_LAYER_DISC_POS(x, y) ((x) | ((y) << 16))
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#define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
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#define ATMEL_HLCDC_LAYER_SCALER_FACTORS(x, y) ((x) | ((y) << 16))
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#define ATMEL_HLCDC_LAYER_SCALER_ENABLE BIT(31)
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#define ATMEL_HLCDC_LAYER_MAX_PLANES 3
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#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED BIT(0)
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#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED BIT(1)
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#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE BIT(2)
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#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN BIT(3)
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#define ATMEL_HLCDC_CLUT_SIZE 256
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#define ATMEL_HLCDC_MAX_LAYERS 6
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/**
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* Atmel HLCDC Layer registers layout structure
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*
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* Each HLCDC layer has its own register organization and a given register
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* can be placed differently on 2 different layers depending on its
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* capabilities.
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* This structure stores common registers layout for a given layer and is
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* used by HLCDC layer code to choose the appropriate register to write to
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* or to read from.
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*
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* For all fields, a value of zero means "unsupported".
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*
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* See Atmel's datasheet for a detailled description of these registers.
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*
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* @xstride: xstride registers
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* @pstride: pstride registers
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* @pos: position register
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* @size: displayed size register
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* @memsize: memory size register
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* @default_color: default color register
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* @chroma_key: chroma key register
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* @chroma_key_mask: chroma key mask register
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* @general_config: general layer config register
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* @sacler_config: scaler factors register
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* @phicoeffs: X/Y PHI coefficient registers
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* @disc_pos: discard area position register
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* @disc_size: discard area size register
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* @csc: color space conversion register
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*/
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struct atmel_hlcdc_layer_cfg_layout {
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int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
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int pstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
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int pos;
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int size;
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int memsize;
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int default_color;
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int chroma_key;
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int chroma_key_mask;
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int general_config;
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int scaler_config;
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struct {
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int x;
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int y;
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} phicoeffs;
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int disc_pos;
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int disc_size;
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int csc;
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};
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/**
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* Atmel HLCDC DMA descriptor structure
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*
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* This structure is used by the HLCDC DMA engine to schedule a DMA transfer.
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*
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* The structure fields must remain in this specific order, because they're
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* used by the HLCDC DMA engine, which expect them in this order.
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* HLCDC DMA descriptors must be aligned on 64 bits.
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*
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* @addr: buffer DMA address
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* @ctrl: DMA transfer options
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* @next: next DMA descriptor to fetch
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* @self: descriptor DMA address
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*/
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struct atmel_hlcdc_dma_channel_dscr {
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dma_addr_t addr;
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u32 ctrl;
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dma_addr_t next;
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dma_addr_t self;
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} __aligned(sizeof(u64));
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/**
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* Atmel HLCDC layer types
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*/
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enum atmel_hlcdc_layer_type {
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ATMEL_HLCDC_NO_LAYER,
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ATMEL_HLCDC_BASE_LAYER,
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ATMEL_HLCDC_OVERLAY_LAYER,
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ATMEL_HLCDC_CURSOR_LAYER,
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ATMEL_HLCDC_PP_LAYER,
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};
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/**
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* Atmel HLCDC Supported formats structure
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*
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* This structure list all the formats supported by a given layer.
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*
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* @nformats: number of supported formats
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* @formats: supported formats
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*/
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struct atmel_hlcdc_formats {
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int nformats;
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u32 *formats;
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};
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/**
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* Atmel HLCDC Layer description structure
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*
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* This structure describes the capabilities provided by a given layer.
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*
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* @name: layer name
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* @type: layer type
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* @id: layer id
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* @regs_offset: offset of the layer registers from the HLCDC registers base
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* @cfgs_offset: CFGX registers offset from the layer registers base
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* @formats: supported formats
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* @layout: config registers layout
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* @max_width: maximum width supported by this layer (0 means unlimited)
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* @max_height: maximum height supported by this layer (0 means unlimited)
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*/
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struct atmel_hlcdc_layer_desc {
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const char *name;
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enum atmel_hlcdc_layer_type type;
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int id;
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int regs_offset;
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int cfgs_offset;
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int clut_offset;
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struct atmel_hlcdc_formats *formats;
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struct atmel_hlcdc_layer_cfg_layout layout;
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int max_width;
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int max_height;
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};
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/**
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* Atmel HLCDC Layer.
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*
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* A layer can be a DRM plane of a post processing layer used to render
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* HLCDC composition into memory.
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*
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* @desc: layer description
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* @regmap: pointer to the HLCDC regmap
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*/
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struct atmel_hlcdc_layer {
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const struct atmel_hlcdc_layer_desc *desc;
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struct regmap *regmap;
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};
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/**
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* Atmel HLCDC Plane.
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*
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* @base: base DRM plane structure
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* @layer: HLCDC layer structure
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* @properties: pointer to the property definitions structure
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*/
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struct atmel_hlcdc_plane {
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struct drm_plane base;
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struct atmel_hlcdc_layer layer;
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};
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static inline struct atmel_hlcdc_plane *
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drm_plane_to_atmel_hlcdc_plane(struct drm_plane *p)
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{
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return container_of(p, struct atmel_hlcdc_plane, base);
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}
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static inline struct atmel_hlcdc_plane *
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atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer)
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{
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return container_of(layer, struct atmel_hlcdc_plane, layer);
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}
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/**
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* Atmel HLCDC Display Controller description structure.
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*
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* This structure describes the HLCDC IP capabilities and depends on the
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* HLCDC IP version (or Atmel SoC family).
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*
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* @min_width: minimum width supported by the Display Controller
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* @min_height: minimum height supported by the Display Controller
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* @max_width: maximum width supported by the Display Controller
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* @max_height: maximum height supported by the Display Controller
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* @max_spw: maximum vertical/horizontal pulse width
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* @max_vpw: maximum vertical back/front porch width
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* @max_hpw: maximum horizontal back/front porch width
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* @conflicting_output_formats: true if RGBXXX output formats conflict with
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* each other.
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* @layers: a layer description table describing available layers
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* @nlayers: layer description table size
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*/
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struct atmel_hlcdc_dc_desc {
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int min_width;
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int min_height;
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int max_width;
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int max_height;
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int max_spw;
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int max_vpw;
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int max_hpw;
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bool conflicting_output_formats;
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const struct atmel_hlcdc_layer_desc *layers;
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int nlayers;
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};
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/**
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* Atmel HLCDC Display Controller.
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*
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* @desc: HLCDC Display Controller description
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* @dscrpool: DMA coherent pool used to allocate DMA descriptors
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* @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
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* @fbdev: framebuffer device attached to the Display Controller
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* @crtc: CRTC provided by the display controller
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* @planes: instantiated planes
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* @layers: active HLCDC layers
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* @wq: display controller workqueue
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* @suspend: used to store the HLCDC state when entering suspend
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* @commit: used for async commit handling
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*/
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struct atmel_hlcdc_dc {
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const struct atmel_hlcdc_dc_desc *desc;
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struct dma_pool *dscrpool;
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struct atmel_hlcdc *hlcdc;
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struct drm_crtc *crtc;
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struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS];
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struct workqueue_struct *wq;
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struct {
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u32 imr;
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struct drm_atomic_state *state;
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} suspend;
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struct {
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wait_queue_head_t wait;
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bool pending;
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} commit;
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};
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extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats;
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extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats;
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static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer,
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unsigned int reg, u32 val)
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{
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regmap_write(layer->regmap, layer->desc->regs_offset + reg, val);
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}
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static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer,
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unsigned int reg)
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{
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u32 val;
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regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val);
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return val;
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}
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static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer,
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unsigned int cfgid, u32 val)
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{
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atmel_hlcdc_layer_write_reg(layer,
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layer->desc->cfgs_offset +
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(cfgid * sizeof(u32)), val);
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}
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static inline u32 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer *layer,
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unsigned int cfgid)
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{
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return atmel_hlcdc_layer_read_reg(layer,
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layer->desc->cfgs_offset +
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(cfgid * sizeof(u32)));
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}
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static inline void atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer *layer,
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unsigned int c, u32 val)
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{
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regmap_write(layer->regmap,
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layer->desc->clut_offset + c * sizeof(u32),
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val);
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}
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static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer,
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const struct atmel_hlcdc_layer_desc *desc,
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struct regmap *regmap)
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{
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layer->desc = desc;
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layer->regmap = regmap;
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}
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enum drm_mode_status
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atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
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const struct drm_display_mode *mode);
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int atmel_hlcdc_create_planes(struct drm_device *dev);
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void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane);
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int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state);
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int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state);
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void atmel_hlcdc_crtc_irq(struct drm_crtc *c);
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int atmel_hlcdc_crtc_create(struct drm_device *dev);
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int atmel_hlcdc_create_outputs(struct drm_device *dev);
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int atmel_hlcdc_encoder_get_bus_fmt(struct drm_encoder *encoder);
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#endif /* DRM_ATMEL_HLCDC_H */
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