677 lines
15 KiB
Plaintext
677 lines
15 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Device Tree Source for AM33xx clock data
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*/
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&scm_clocks {
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sys_clkin_ck: sys_clkin_ck@40 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
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ti,bit-shift = <22>;
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reg = <0x0040>;
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};
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adc_tsc_fck: adc_tsc_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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dcan0_fck: dcan0_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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dcan1_fck: dcan1_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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mcasp0_fck: mcasp0_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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mcasp1_fck: mcasp1_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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smartreflex0_fck: smartreflex0_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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smartreflex1_fck: smartreflex1_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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sha0_fck: sha0_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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aes0_fck: aes0_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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rng_fck: rng_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l4ls_gclk>;
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ti,bit-shift = <0>;
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reg = <0x0664>;
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};
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ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l4ls_gclk>;
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ti,bit-shift = <1>;
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reg = <0x0664>;
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};
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ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l4ls_gclk>;
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ti,bit-shift = <2>;
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reg = <0x0664>;
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};
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};
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&prcm_clocks {
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clk_32768_ck: clk_32768_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_rc32k_ck: clk_rc32k_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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virt_19200000_ck: virt_19200000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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};
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virt_24000000_ck: virt_24000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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virt_25000000_ck: virt_25000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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virt_26000000_ck: virt_26000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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};
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tclkin_ck: tclkin_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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};
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dpll_core_ck: dpll_core_ck@490 {
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#clock-cells = <0>;
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compatible = "ti,am3-dpll-core-clock";
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clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
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reg = <0x0490>, <0x045c>, <0x0468>;
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};
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dpll_core_x2_ck: dpll_core_x2_ck {
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#clock-cells = <0>;
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compatible = "ti,am3-dpll-x2-clock";
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clocks = <&dpll_core_ck>;
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};
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dpll_core_m4_ck: dpll_core_m4_ck@480 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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reg = <0x0480>;
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ti,index-starts-at-one;
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};
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dpll_core_m5_ck: dpll_core_m5_ck@484 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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reg = <0x0484>;
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ti,index-starts-at-one;
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};
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dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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reg = <0x04d8>;
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ti,index-starts-at-one;
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};
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dpll_mpu_ck: dpll_mpu_ck@488 {
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#clock-cells = <0>;
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compatible = "ti,am3-dpll-clock";
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clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
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reg = <0x0488>, <0x0420>, <0x042c>;
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};
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dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_mpu_ck>;
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ti,max-div = <31>;
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reg = <0x04a8>;
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ti,index-starts-at-one;
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};
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dpll_ddr_ck: dpll_ddr_ck@494 {
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#clock-cells = <0>;
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compatible = "ti,am3-dpll-no-gate-clock";
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clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
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reg = <0x0494>, <0x0434>, <0x0440>;
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};
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dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_ddr_ck>;
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ti,max-div = <31>;
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reg = <0x04a0>;
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ti,index-starts-at-one;
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};
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dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_ddr_m2_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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dpll_disp_ck: dpll_disp_ck@498 {
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#clock-cells = <0>;
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compatible = "ti,am3-dpll-no-gate-clock";
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clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
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reg = <0x0498>, <0x0448>, <0x0454>;
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};
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dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_disp_ck>;
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ti,max-div = <31>;
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reg = <0x04a4>;
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ti,index-starts-at-one;
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ti,set-rate-parent;
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};
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dpll_per_ck: dpll_per_ck@48c {
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#clock-cells = <0>;
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compatible = "ti,am3-dpll-no-gate-j-type-clock";
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clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
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reg = <0x048c>, <0x0470>, <0x049c>;
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};
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dpll_per_m2_ck: dpll_per_m2_ck@4ac {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_per_ck>;
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ti,max-div = <31>;
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reg = <0x04ac>;
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ti,index-starts-at-one;
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};
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dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_per_m2_ck>;
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clock-mult = <1>;
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clock-div = <4>;
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};
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dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_per_m2_ck>;
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clock-mult = <1>;
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clock-div = <4>;
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};
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clk_24mhz: clk_24mhz {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_per_m2_ck>;
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clock-mult = <1>;
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clock-div = <8>;
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};
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clkdiv32k_ck: clkdiv32k_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_24mhz>;
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clock-mult = <1>;
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clock-div = <732>;
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};
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l3_gclk: l3_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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pruss_ocp_gclk: pruss_ocp_gclk@530 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
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reg = <0x0530>;
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};
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mmu_fck: mmu_fck@914 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_core_m4_ck>;
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ti,bit-shift = <1>;
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reg = <0x0914>;
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};
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timer1_fck: timer1_fck@528 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
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reg = <0x0528>;
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};
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timer2_fck: timer2_fck@508 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x0508>;
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};
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timer3_fck: timer3_fck@50c {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x050c>;
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};
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timer4_fck: timer4_fck@510 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x0510>;
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};
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timer5_fck: timer5_fck@518 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x0518>;
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};
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timer6_fck: timer6_fck@51c {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x051c>;
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};
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timer7_fck: timer7_fck@504 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x0504>;
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};
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usbotg_fck: usbotg_fck@47c {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_ck>;
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ti,bit-shift = <8>;
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reg = <0x047c>;
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};
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dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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ieee5000_fck: ieee5000_fck@e4 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_core_m4_div2_ck>;
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ti,bit-shift = <1>;
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reg = <0x00e4>;
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};
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wdt1_fck: wdt1_fck@538 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x0538>;
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};
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l4_rtc_gclk: l4_rtc_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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l4hs_gclk: l4hs_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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l3s_gclk: l3s_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_div2_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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l4fw_gclk: l4fw_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_div2_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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l4ls_gclk: l4ls_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_div2_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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sysclk_div_ck: sysclk_div_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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cpsw_125mhz_gclk: cpsw_125mhz_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m5_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
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reg = <0x0520>;
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};
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gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x053c>;
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};
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lcd_gclk: lcd_gclk@534 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
|
|
reg = <0x0534>;
|
|
ti,set-rate-parent;
|
|
};
|
|
|
|
mmc_clk: mmc_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_per_m2_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <2>;
|
|
};
|
|
|
|
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x052c>;
|
|
};
|
|
|
|
gfx_fck_div_ck: gfx_fck_div_ck@52c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&gfx_fclk_clksel_ck>;
|
|
reg = <0x052c>;
|
|
ti,max-div = <2>;
|
|
};
|
|
|
|
sysclkout_pre_ck: sysclkout_pre_ck@700 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
|
|
reg = <0x0700>;
|
|
};
|
|
|
|
clkout2_div_ck: clkout2_div_ck@700 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&sysclkout_pre_ck>;
|
|
ti,bit-shift = <3>;
|
|
ti,max-div = <8>;
|
|
reg = <0x0700>;
|
|
};
|
|
|
|
clkout2_ck: clkout2_ck@700 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&clkout2_div_ck>;
|
|
ti,bit-shift = <7>;
|
|
reg = <0x0700>;
|
|
};
|
|
};
|
|
|
|
&prcm {
|
|
per_cm: per-cm@0 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x0 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x0 0x400>;
|
|
|
|
l4ls_clkctrl: l4ls-clkctrl@38 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
|
|
l3s_clkctrl: l3s-clkctrl@1c {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
|
|
l3_clkctrl: l3-clkctrl@24 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
|
|
#clock-cells = <2>;
|
|
};
|
|
|
|
l4hs_clkctrl: l4hs-clkctrl@120 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x120 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
|
|
pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0xe8 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
|
|
cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x0 0x18>;
|
|
#clock-cells = <2>;
|
|
};
|
|
|
|
lcdc_clkctrl: lcdc-clkctrl@18 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x18 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
|
|
clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x14c 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
wkup_cm: wkup-cm@400 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x400 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x400 0x100>;
|
|
|
|
l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x0 0x10>, <0xb4 0x24>;
|
|
#clock-cells = <2>;
|
|
};
|
|
|
|
l3_aon_clkctrl: l3-aon-clkctrl@14 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x14 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
|
|
l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0xb0 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
mpu_cm: mpu-cm@600 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x600 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x600 0x100>;
|
|
|
|
mpu_clkctrl: mpu-clkctrl@0 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x0 0x8>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
l4_rtc_cm: l4-rtc-cm@800 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x800 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x800 0x100>;
|
|
|
|
l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x0 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
gfx_l3_cm: gfx-l3-cm@900 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x900 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x900 0x100>;
|
|
|
|
gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x0 0x8>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
l4_cefuse_cm: l4-cefuse-cm@a00 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0xa00 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0xa00 0x100>;
|
|
|
|
l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x0 0x24>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
};
|