452 lines
11 KiB
C
452 lines
11 KiB
C
/*
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* Qualcomm SCM driver
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*
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* Copyright (c) 2010,2015, The Linux Foundation. All rights reserved.
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* Copyright (C) 2015 Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/cpumask.h>
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#include <linux/export.h>
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#include <linux/dma-mapping.h>
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#include <linux/types.h>
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#include <linux/qcom_scm.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/clk.h>
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#include <linux/reset-controller.h>
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#include "qcom_scm.h"
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#define SCM_HAS_CORE_CLK BIT(0)
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#define SCM_HAS_IFACE_CLK BIT(1)
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#define SCM_HAS_BUS_CLK BIT(2)
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struct qcom_scm {
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struct device *dev;
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struct clk *core_clk;
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struct clk *iface_clk;
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struct clk *bus_clk;
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struct reset_controller_dev reset;
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};
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static struct qcom_scm *__scm;
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static int qcom_scm_clk_enable(void)
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{
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int ret;
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ret = clk_prepare_enable(__scm->core_clk);
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if (ret)
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goto bail;
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ret = clk_prepare_enable(__scm->iface_clk);
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if (ret)
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goto disable_core;
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ret = clk_prepare_enable(__scm->bus_clk);
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if (ret)
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goto disable_iface;
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return 0;
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disable_iface:
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clk_disable_unprepare(__scm->iface_clk);
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disable_core:
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clk_disable_unprepare(__scm->core_clk);
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bail:
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return ret;
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}
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static void qcom_scm_clk_disable(void)
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{
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clk_disable_unprepare(__scm->core_clk);
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clk_disable_unprepare(__scm->iface_clk);
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clk_disable_unprepare(__scm->bus_clk);
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}
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/**
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* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
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* @entry: Entry point function for the cpus
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* @cpus: The cpumask of cpus that will use the entry point
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*
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* Set the cold boot address of the cpus. Any cpu outside the supported
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* range would be removed from the cpu present mask.
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*/
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int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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{
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return __qcom_scm_set_cold_boot_addr(entry, cpus);
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}
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EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
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/**
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* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
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* @entry: Entry point function for the cpus
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* @cpus: The cpumask of cpus that will use the entry point
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*
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* Set the Linux entry point for the SCM to transfer control to when coming
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* out of a power down. CPU power down may be executed on cpuidle or hotplug.
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*/
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int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
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{
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return __qcom_scm_set_warm_boot_addr(__scm->dev, entry, cpus);
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}
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EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
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/**
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* qcom_scm_cpu_power_down() - Power down the cpu
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* @flags - Flags to flush cache
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*
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* This is an end point to power down cpu. If there was a pending interrupt,
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* the control would return from this function, otherwise, the cpu jumps to the
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* warm boot entry point set for this cpu upon reset.
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*/
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void qcom_scm_cpu_power_down(u32 flags)
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{
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__qcom_scm_cpu_power_down(flags);
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}
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EXPORT_SYMBOL(qcom_scm_cpu_power_down);
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/**
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* qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
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*
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* Return true if HDCP is supported, false if not.
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*/
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bool qcom_scm_hdcp_available(void)
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{
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int ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
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QCOM_SCM_CMD_HDCP);
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qcom_scm_clk_disable();
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return ret > 0 ? true : false;
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}
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EXPORT_SYMBOL(qcom_scm_hdcp_available);
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/**
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* qcom_scm_hdcp_req() - Send HDCP request.
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* @req: HDCP request array
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* @req_cnt: HDCP request array count
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* @resp: response buffer passed to SCM
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*
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* Write HDCP register(s) through SCM.
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*/
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int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
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{
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int ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = __qcom_scm_hdcp_req(__scm->dev, req, req_cnt, resp);
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qcom_scm_clk_disable();
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return ret;
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}
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EXPORT_SYMBOL(qcom_scm_hdcp_req);
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/**
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* qcom_scm_pas_supported() - Check if the peripheral authentication service is
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* available for the given peripherial
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* @peripheral: peripheral id
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*
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* Returns true if PAS is supported for this peripheral, otherwise false.
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*/
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bool qcom_scm_pas_supported(u32 peripheral)
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{
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int ret;
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ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PAS_IS_SUPPORTED_CMD);
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if (ret <= 0)
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return false;
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return __qcom_scm_pas_supported(__scm->dev, peripheral);
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}
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EXPORT_SYMBOL(qcom_scm_pas_supported);
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/**
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* qcom_scm_pas_init_image() - Initialize peripheral authentication service
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* state machine for a given peripheral, using the
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* metadata
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* @peripheral: peripheral id
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* @metadata: pointer to memory containing ELF header, program header table
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* and optional blob of data used for authenticating the metadata
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* and the rest of the firmware
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* @size: size of the metadata
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*
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* Returns 0 on success.
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*/
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int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size)
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{
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dma_addr_t mdata_phys;
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void *mdata_buf;
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int ret;
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/*
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* During the scm call memory protection will be enabled for the meta
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* data blob, so make sure it's physically contiguous, 4K aligned and
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* non-cachable to avoid XPU violations.
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*/
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mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys,
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GFP_KERNEL);
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if (!mdata_buf) {
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dev_err(__scm->dev, "Allocation of metadata buffer failed.\n");
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return -ENOMEM;
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}
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memcpy(mdata_buf, metadata, size);
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ret = qcom_scm_clk_enable();
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if (ret)
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goto free_metadata;
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ret = __qcom_scm_pas_init_image(__scm->dev, peripheral, mdata_phys);
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qcom_scm_clk_disable();
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free_metadata:
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dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys);
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return ret;
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}
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EXPORT_SYMBOL(qcom_scm_pas_init_image);
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/**
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* qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
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* for firmware loading
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* @peripheral: peripheral id
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* @addr: start address of memory area to prepare
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* @size: size of the memory area to prepare
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*
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* Returns 0 on success.
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*/
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int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
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{
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int ret;
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ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = __qcom_scm_pas_mem_setup(__scm->dev, peripheral, addr, size);
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qcom_scm_clk_disable();
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return ret;
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}
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EXPORT_SYMBOL(qcom_scm_pas_mem_setup);
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/**
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* qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
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* and reset the remote processor
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* @peripheral: peripheral id
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*
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* Return 0 on success.
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*/
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int qcom_scm_pas_auth_and_reset(u32 peripheral)
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{
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int ret;
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ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = __qcom_scm_pas_auth_and_reset(__scm->dev, peripheral);
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qcom_scm_clk_disable();
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return ret;
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}
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EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset);
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/**
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* qcom_scm_pas_shutdown() - Shut down the remote processor
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* @peripheral: peripheral id
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*
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* Returns 0 on success.
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*/
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int qcom_scm_pas_shutdown(u32 peripheral)
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{
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int ret;
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ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = __qcom_scm_pas_shutdown(__scm->dev, peripheral);
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qcom_scm_clk_disable();
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return ret;
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}
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EXPORT_SYMBOL(qcom_scm_pas_shutdown);
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static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long idx)
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{
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if (idx != 0)
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return -EINVAL;
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return __qcom_scm_pas_mss_reset(__scm->dev, 1);
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}
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static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long idx)
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{
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if (idx != 0)
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return -EINVAL;
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return __qcom_scm_pas_mss_reset(__scm->dev, 0);
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}
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static const struct reset_control_ops qcom_scm_pas_reset_ops = {
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.assert = qcom_scm_pas_reset_assert,
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.deassert = qcom_scm_pas_reset_deassert,
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};
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/**
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* qcom_scm_is_available() - Checks if SCM is available
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*/
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bool qcom_scm_is_available(void)
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{
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return !!__scm;
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}
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EXPORT_SYMBOL(qcom_scm_is_available);
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int qcom_scm_set_remote_state(u32 state, u32 id)
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{
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return __qcom_scm_set_remote_state(__scm->dev, state, id);
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}
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EXPORT_SYMBOL(qcom_scm_set_remote_state);
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static int qcom_scm_probe(struct platform_device *pdev)
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{
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struct qcom_scm *scm;
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unsigned long clks;
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int ret;
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scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
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if (!scm)
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return -ENOMEM;
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clks = (unsigned long)of_device_get_match_data(&pdev->dev);
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if (clks & SCM_HAS_CORE_CLK) {
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scm->core_clk = devm_clk_get(&pdev->dev, "core");
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if (IS_ERR(scm->core_clk)) {
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if (PTR_ERR(scm->core_clk) != -EPROBE_DEFER)
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dev_err(&pdev->dev,
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"failed to acquire core clk\n");
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return PTR_ERR(scm->core_clk);
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}
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}
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if (clks & SCM_HAS_IFACE_CLK) {
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scm->iface_clk = devm_clk_get(&pdev->dev, "iface");
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if (IS_ERR(scm->iface_clk)) {
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if (PTR_ERR(scm->iface_clk) != -EPROBE_DEFER)
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dev_err(&pdev->dev,
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"failed to acquire iface clk\n");
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return PTR_ERR(scm->iface_clk);
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}
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}
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if (clks & SCM_HAS_BUS_CLK) {
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scm->bus_clk = devm_clk_get(&pdev->dev, "bus");
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if (IS_ERR(scm->bus_clk)) {
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if (PTR_ERR(scm->bus_clk) != -EPROBE_DEFER)
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dev_err(&pdev->dev,
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"failed to acquire bus clk\n");
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return PTR_ERR(scm->bus_clk);
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}
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}
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scm->reset.ops = &qcom_scm_pas_reset_ops;
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scm->reset.nr_resets = 1;
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scm->reset.of_node = pdev->dev.of_node;
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ret = devm_reset_controller_register(&pdev->dev, &scm->reset);
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if (ret)
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return ret;
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/* vote for max clk rate for highest performance */
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ret = clk_set_rate(scm->core_clk, INT_MAX);
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if (ret)
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return ret;
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__scm = scm;
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__scm->dev = &pdev->dev;
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__qcom_scm_init();
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return 0;
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}
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static const struct of_device_id qcom_scm_dt_match[] = {
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{ .compatible = "qcom,scm-apq8064",
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/* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */
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},
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{ .compatible = "qcom,scm-msm8660",
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.data = (void *) SCM_HAS_CORE_CLK,
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},
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{ .compatible = "qcom,scm-msm8960",
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.data = (void *) SCM_HAS_CORE_CLK,
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},
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{ .compatible = "qcom,scm-msm8996",
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.data = NULL, /* no clocks */
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},
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{ .compatible = "qcom,scm",
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.data = (void *)(SCM_HAS_CORE_CLK
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| SCM_HAS_IFACE_CLK
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| SCM_HAS_BUS_CLK),
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},
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{}
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};
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static struct platform_driver qcom_scm_driver = {
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.driver = {
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.name = "qcom_scm",
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.of_match_table = qcom_scm_dt_match,
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},
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.probe = qcom_scm_probe,
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};
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static int __init qcom_scm_init(void)
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{
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struct device_node *np, *fw_np;
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int ret;
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fw_np = of_find_node_by_name(NULL, "firmware");
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if (!fw_np)
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return -ENODEV;
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np = of_find_matching_node(fw_np, qcom_scm_dt_match);
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if (!np) {
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of_node_put(fw_np);
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return -ENODEV;
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}
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of_node_put(np);
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ret = of_platform_populate(fw_np, qcom_scm_dt_match, NULL, NULL);
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of_node_put(fw_np);
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if (ret)
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return ret;
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return platform_driver_register(&qcom_scm_driver);
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}
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subsys_initcall(qcom_scm_init);
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