158 lines
4.8 KiB
C
158 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 Collabora Ltd.
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* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt6795-clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-pll.h"
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#define REG_REF2USB 0x8
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#define REG_AP_PLL_CON7 0x1c
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#define MD1_MTCMOS_OFF BIT(0)
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#define MD1_MEM_OFF BIT(1)
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#define MD1_CLK_OFF BIT(4)
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#define MD1_ISO_OFF BIT(8)
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#define MT6795_PLL_FMAX (3000UL * MHZ)
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#define MT6795_CON0_EN BIT(0)
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#define MT6795_CON0_RST_BAR BIT(24)
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = MT6795_CON0_EN | _en_mask, \
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.flags = _flags, \
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.rst_bar_mask = MT6795_CON0_RST_BAR, \
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.fmax = MT6795_PLL_FMAX, \
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.pcwbits = _pcwbits, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.div_table = NULL, \
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.pll_en_bit = 0, \
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}
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static const struct mtk_pll_data plls[] = {
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PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,
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21, 0x204, 24, 0x0, 0x204, 0),
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PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
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21, 0x220, 4, 0x0, 0x224, 0),
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PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,
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7, 0x230, 4, 0x0, 0x234, 14),
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PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0),
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PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
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PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
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PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
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PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
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PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0),
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PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a8, 0x2a4, 0),
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PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2bc, 0x2b8, 0),
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};
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static void clk_mt6795_apmixed_setup_md1(void __iomem *base)
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{
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void __iomem *reg = base + REG_AP_PLL_CON7;
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/* Turn on MD1 internal clock */
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writel(readl(reg) & ~MD1_CLK_OFF, reg);
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/* Unlock MD1's MTCMOS power path */
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writel(readl(reg) & ~MD1_MTCMOS_OFF, reg);
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/* Turn on ISO */
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writel(readl(reg) & ~MD1_ISO_OFF, reg);
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/* Turn on memory */
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writel(readl(reg) & ~MD1_MEM_OFF, reg);
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}
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static const struct of_device_id of_match_clk_mt6795_apmixed[] = {
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{ .compatible = "mediatek,mt6795-apmixedsys" },
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{ /* sentinel */ }
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};
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static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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void __iomem *base;
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struct clk_hw *hw;
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int ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
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if (ret)
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goto free_clk_data;
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hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REG_REF2USB);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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dev_err(dev, "Failed to register ref2usb_tx: %d\n", ret);
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goto unregister_plls;
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}
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clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw;
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (ret) {
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dev_err(dev, "Cannot register clock provider: %d\n", ret);
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goto unregister_ref2usb;
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}
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/* Setup MD1 to avoid random crashes */
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dev_dbg(dev, "Performing initial setup for MD1\n");
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clk_mt6795_apmixed_setup_md1(base);
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return 0;
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unregister_ref2usb:
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mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
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unregister_plls:
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mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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return ret;
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}
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static int clk_mt6795_apmixed_remove(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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of_clk_del_provider(node);
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mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
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mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
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mtk_free_clk_data(clk_data);
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return 0;
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}
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static struct platform_driver clk_mt6795_apmixed_drv = {
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.probe = clk_mt6795_apmixed_probe,
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.remove = clk_mt6795_apmixed_remove,
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.driver = {
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.name = "clk-mt6795-apmixed",
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.of_match_table = of_match_clk_mt6795_apmixed,
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},
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};
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module_platform_driver(clk_mt6795_apmixed_drv);
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MODULE_DESCRIPTION("MediaTek MT6795 apmixed clocks driver");
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MODULE_LICENSE("GPL");
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