99 lines
3.7 KiB
C
99 lines
3.7 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _GVT_REG_H
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#define _GVT_REG_H
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#define INTEL_GVT_PCI_CLASS_VGA_OTHER 0x80
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#define INTEL_GVT_PCI_GMCH_CONTROL 0x50
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#define BDW_GMCH_GMS_SHIFT 8
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#define BDW_GMCH_GMS_MASK 0xff
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#define INTEL_GVT_PCI_SWSCI 0xe8
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#define SWSCI_SCI_SELECT (1 << 15)
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#define SWSCI_SCI_TRIGGER 1
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#define INTEL_GVT_PCI_OPREGION 0xfc
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#define INTEL_GVT_OPREGION_CLID 0x1AC
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#define INTEL_GVT_OPREGION_SCIC 0x200
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#define OPREGION_SCIC_FUNC_MASK 0x1E
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#define OPREGION_SCIC_FUNC_SHIFT 1
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#define OPREGION_SCIC_SUBFUNC_MASK 0xFF00
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#define OPREGION_SCIC_SUBFUNC_SHIFT 8
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#define OPREGION_SCIC_EXIT_MASK 0xE0
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#define INTEL_GVT_OPREGION_SCIC_F_GETBIOSDATA 4
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#define INTEL_GVT_OPREGION_SCIC_F_GETBIOSCALLBACKS 6
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#define INTEL_GVT_OPREGION_SCIC_SF_SUPPRTEDCALLS 0
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#define INTEL_GVT_OPREGION_SCIC_SF_REQEUSTEDCALLBACKS 1
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#define INTEL_GVT_OPREGION_PARM 0x204
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#define INTEL_GVT_OPREGION_PAGES 2
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#define INTEL_GVT_OPREGION_SIZE (INTEL_GVT_OPREGION_PAGES * PAGE_SIZE)
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#define INTEL_GVT_OPREGION_VBT_OFFSET 0x400
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#define INTEL_GVT_OPREGION_VBT_SIZE \
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(INTEL_GVT_OPREGION_SIZE - INTEL_GVT_OPREGION_VBT_OFFSET)
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#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
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#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100)
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#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
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#define GFX_MODE_BIT_SET_IN_MASK(val, bit) \
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((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16))))
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#define FORCEWAKE_RENDER_GEN9_REG 0xa278
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#define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84
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#define FORCEWAKE_BLITTER_GEN9_REG 0xa188
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#define FORCEWAKE_ACK_BLITTER_GEN9_REG 0x130044
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#define FORCEWAKE_MEDIA_GEN9_REG 0xa270
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#define FORCEWAKE_ACK_MEDIA_GEN9_REG 0x0D88
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#define FORCEWAKE_ACK_HSW_REG 0x130044
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#define RB_HEAD_OFF_MASK ((1U << 21) - (1U << 2))
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#define RB_TAIL_OFF_MASK ((1U << 21) - (1U << 3))
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#define RB_TAIL_SIZE_MASK ((1U << 21) - (1U << 12))
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#define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
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I915_GTT_PAGE_SIZE)
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#define PCH_GPIO_BASE _MMIO(0xc5010)
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#define PCH_GMBUS0 _MMIO(0xc5100)
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#define PCH_GMBUS1 _MMIO(0xc5104)
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#define PCH_GMBUS2 _MMIO(0xc5108)
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#define PCH_GMBUS3 _MMIO(0xc510c)
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#define PCH_GMBUS4 _MMIO(0xc5110)
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#define PCH_GMBUS5 _MMIO(0xc5120)
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#define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i) * 4)
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#define TRNULLDETCT _MMIO(0x4de8)
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#define TRINVTILEDETCT _MMIO(0x4dec)
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#define TRVADR _MMIO(0x4df0)
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#define TRTTE _MMIO(0x4df4)
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#define RING_EXCC(base) _MMIO((base) + 0x28)
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#define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
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#define VF_GUARDBAND _MMIO(0x83a4)
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#endif
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