196 lines
6.2 KiB
C
196 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* bpf_jit.h: BPF JIT compiler for PPC
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*
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* Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation
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* 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
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*/
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#ifndef _BPF_JIT_H
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#define _BPF_JIT_H
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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#include <asm/ppc-opcode.h>
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#ifdef PPC64_ELF_ABI_v1
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#define FUNCTION_DESCR_SIZE 24
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#else
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#define FUNCTION_DESCR_SIZE 0
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#endif
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#define PLANT_INSTR(d, idx, instr) \
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do { if (d) { (d)[idx] = instr; } idx++; } while (0)
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#define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr)
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/* Long jump; (unconditional 'branch') */
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#define PPC_JMP(dest) \
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do { \
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long offset = (long)(dest) - (ctx->idx * 4); \
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if (!is_offset_in_branch_range(offset)) { \
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pr_err_ratelimited("Branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \
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return -ERANGE; \
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} \
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EMIT(PPC_RAW_BRANCH(offset)); \
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} while (0)
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/* blr; (unconditional 'branch' with link) to absolute address */
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#define PPC_BL_ABS(dest) EMIT(PPC_INST_BL | \
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(((dest) - (unsigned long)(image + ctx->idx)) & 0x03fffffc))
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/* "cond" here covers BO:BI fields. */
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#define PPC_BCC_SHORT(cond, dest) \
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do { \
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long offset = (long)(dest) - (ctx->idx * 4); \
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if (!is_offset_in_cond_branch_range(offset)) { \
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pr_err_ratelimited("Conditional branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \
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return -ERANGE; \
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} \
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EMIT(PPC_INST_BRANCH_COND | (((cond) & 0x3ff) << 16) | (offset & 0xfffc)); \
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} while (0)
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/* Sign-extended 32-bit immediate load */
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#define PPC_LI32(d, i) do { \
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if ((int)(uintptr_t)(i) >= -32768 && \
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(int)(uintptr_t)(i) < 32768) \
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EMIT(PPC_RAW_LI(d, i)); \
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else { \
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EMIT(PPC_RAW_LIS(d, IMM_H(i))); \
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if (IMM_L(i)) \
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EMIT(PPC_RAW_ORI(d, d, IMM_L(i))); \
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} } while(0)
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#ifdef CONFIG_PPC32
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#define PPC_EX32(r, i) EMIT(PPC_RAW_LI((r), (i) < 0 ? -1 : 0))
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#endif
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#define PPC_LI64(d, i) do { \
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if ((long)(i) >= -2147483648 && \
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(long)(i) < 2147483648) \
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PPC_LI32(d, i); \
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else { \
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if (!((uintptr_t)(i) & 0xffff800000000000ULL)) \
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EMIT(PPC_RAW_LI(d, ((uintptr_t)(i) >> 32) & \
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0xffff)); \
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else { \
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EMIT(PPC_RAW_LIS(d, ((uintptr_t)(i) >> 48))); \
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if ((uintptr_t)(i) & 0x0000ffff00000000ULL) \
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EMIT(PPC_RAW_ORI(d, d, \
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((uintptr_t)(i) >> 32) & 0xffff)); \
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} \
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EMIT(PPC_RAW_SLDI(d, d, 32)); \
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if ((uintptr_t)(i) & 0x00000000ffff0000ULL) \
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EMIT(PPC_RAW_ORIS(d, d, \
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((uintptr_t)(i) >> 16) & 0xffff)); \
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if ((uintptr_t)(i) & 0x000000000000ffffULL) \
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EMIT(PPC_RAW_ORI(d, d, (uintptr_t)(i) & \
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0xffff)); \
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} } while (0)
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#ifdef CONFIG_PPC64
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#define PPC_FUNC_ADDR(d,i) do { PPC_LI64(d, i); } while(0)
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#else
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#define PPC_FUNC_ADDR(d,i) do { PPC_LI32(d, i); } while(0)
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#endif
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/*
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* The fly in the ointment of code size changing from pass to pass is
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* avoided by padding the short branch case with a NOP. If code size differs
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* with different branch reaches we will have the issue of code moving from
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* one pass to the next and will need a few passes to converge on a stable
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* state.
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*/
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#define PPC_BCC(cond, dest) do { \
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if (is_offset_in_cond_branch_range((long)(dest) - (ctx->idx * 4))) { \
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PPC_BCC_SHORT(cond, dest); \
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EMIT(PPC_RAW_NOP()); \
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} else { \
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/* Flip the 'T or F' bit to invert comparison */ \
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PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4); \
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PPC_JMP(dest); \
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} } while(0)
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/* To create a branch condition, select a bit of cr0... */
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#define CR0_LT 0
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#define CR0_GT 1
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#define CR0_EQ 2
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/* ...and modify BO[3] */
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#define COND_CMP_TRUE 0x100
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#define COND_CMP_FALSE 0x000
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/* Together, they make all required comparisons: */
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#define COND_GT (CR0_GT | COND_CMP_TRUE)
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#define COND_GE (CR0_LT | COND_CMP_FALSE)
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#define COND_EQ (CR0_EQ | COND_CMP_TRUE)
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#define COND_NE (CR0_EQ | COND_CMP_FALSE)
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#define COND_LT (CR0_LT | COND_CMP_TRUE)
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#define COND_LE (CR0_GT | COND_CMP_FALSE)
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#define SEEN_FUNC 0x20000000 /* might call external helpers */
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#define SEEN_TAILCALL 0x40000000 /* uses tail calls */
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#define SEEN_VREG_MASK 0x1ff80000 /* Volatile registers r3-r12 */
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#define SEEN_NVREG_MASK 0x0003ffff /* Non volatile registers r14-r31 */
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#ifdef CONFIG_PPC64
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extern const int b2p[MAX_BPF_JIT_REG + 2];
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#else
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extern const int b2p[MAX_BPF_JIT_REG + 1];
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#endif
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struct codegen_context {
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/*
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* This is used to track register usage as well
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* as calls to external helpers.
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* - register usage is tracked with corresponding
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* bits (r3-r31)
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* - rest of the bits can be used to track other
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* things -- for now, we use bits 0 to 2
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* encoded in SEEN_* macros above
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*/
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unsigned int seen;
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unsigned int idx;
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unsigned int stack_size;
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int b2p[ARRAY_SIZE(b2p)];
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unsigned int exentry_idx;
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};
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#ifdef CONFIG_PPC32
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#define BPF_FIXUP_LEN 3 /* Three instructions => 12 bytes */
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#else
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#define BPF_FIXUP_LEN 2 /* Two instructions => 8 bytes */
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#endif
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static inline void bpf_flush_icache(void *start, void *end)
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{
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smp_wmb(); /* smp write barrier */
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flush_icache_range((unsigned long)start, (unsigned long)end);
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}
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static inline bool bpf_is_seen_register(struct codegen_context *ctx, int i)
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{
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return ctx->seen & (1 << (31 - i));
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}
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static inline void bpf_set_seen_register(struct codegen_context *ctx, int i)
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{
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ctx->seen |= 1 << (31 - i);
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}
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static inline void bpf_clear_seen_register(struct codegen_context *ctx, int i)
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{
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ctx->seen &= ~(1 << (31 - i));
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}
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void bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 func);
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int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *ctx,
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u32 *addrs, int pass);
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void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx);
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void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx);
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void bpf_jit_realloc_regs(struct codegen_context *ctx);
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int bpf_add_extable_entry(struct bpf_prog *fp, u32 *image, int pass, struct codegen_context *ctx,
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int insn_idx, int jmp_off, int dst_reg);
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#endif
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#endif
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