404 lines
10 KiB
C
404 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* irqchip for the IXP4xx interrupt controller
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* Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
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*
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* Based on arch/arm/mach-ixp4xx/common.c
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* Copyright 2002 (C) Intel Corporation
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* Copyright 2003-2004 (C) MontaVista, Software, Inc.
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* Copyright (C) Deepak Saxena <dsaxena@plexity.net>
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*/
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#include <linux/bitops.h>
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#include <linux/gpio/driver.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/irq-ixp4xx.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/cpu.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#define IXP4XX_ICPR 0x00 /* Interrupt Status */
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#define IXP4XX_ICMR 0x04 /* Interrupt Enable */
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#define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
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#define IXP4XX_ICIP 0x0C /* IRQ Status */
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#define IXP4XX_ICFP 0x10 /* FIQ Status */
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#define IXP4XX_ICHR 0x14 /* Interrupt Priority */
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#define IXP4XX_ICIH 0x18 /* IRQ Highest Pri Int */
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#define IXP4XX_ICFH 0x1C /* FIQ Highest Pri Int */
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/* IXP43x and IXP46x-only */
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#define IXP4XX_ICPR2 0x20 /* Interrupt Status 2 */
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#define IXP4XX_ICMR2 0x24 /* Interrupt Enable 2 */
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#define IXP4XX_ICLR2 0x28 /* Interrupt IRQ/FIQ Select 2 */
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#define IXP4XX_ICIP2 0x2C /* IRQ Status */
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#define IXP4XX_ICFP2 0x30 /* FIQ Status */
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#define IXP4XX_ICEEN 0x34 /* Error High Pri Enable */
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/**
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* struct ixp4xx_irq - state container for the Faraday IRQ controller
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* @irqbase: IRQ controller memory base in virtual memory
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* @is_356: if this is an IXP43x, IXP45x or IX46x SoC (with 64 IRQs)
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* @irqchip: irqchip for this instance
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* @domain: IRQ domain for this instance
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*/
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struct ixp4xx_irq {
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void __iomem *irqbase;
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bool is_356;
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struct irq_chip irqchip;
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struct irq_domain *domain;
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};
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/* Local static state container */
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static struct ixp4xx_irq ixirq;
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/* GPIO Clocks */
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#define IXP4XX_GPIO_CLK_0 14
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#define IXP4XX_GPIO_CLK_1 15
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static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
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{
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/* All are level active high (asserted) here */
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if (type != IRQ_TYPE_LEVEL_HIGH)
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return -EINVAL;
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return 0;
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}
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static void ixp4xx_irq_mask(struct irq_data *d)
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{
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struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
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u32 val;
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if (ixi->is_356 && d->hwirq >= 32) {
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val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
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val &= ~BIT(d->hwirq - 32);
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__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
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} else {
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val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
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val &= ~BIT(d->hwirq);
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__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
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}
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}
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/*
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* Level triggered interrupts on GPIO lines can only be cleared when the
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* interrupt condition disappears.
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*/
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static void ixp4xx_irq_unmask(struct irq_data *d)
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{
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struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
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u32 val;
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if (ixi->is_356 && d->hwirq >= 32) {
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val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
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val |= BIT(d->hwirq - 32);
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__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
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} else {
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val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
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val |= BIT(d->hwirq);
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__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
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}
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}
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asmlinkage void __exception_irq_entry ixp4xx_handle_irq(struct pt_regs *regs)
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{
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struct ixp4xx_irq *ixi = &ixirq;
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unsigned long status;
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int i;
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status = __raw_readl(ixi->irqbase + IXP4XX_ICIP);
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for_each_set_bit(i, &status, 32)
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handle_domain_irq(ixi->domain, i, regs);
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/*
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* IXP465/IXP435 has an upper IRQ status register
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*/
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if (ixi->is_356) {
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status = __raw_readl(ixi->irqbase + IXP4XX_ICIP2);
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for_each_set_bit(i, &status, 32)
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handle_domain_irq(ixi->domain, i + 32, regs);
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}
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}
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static int ixp4xx_irq_domain_translate(struct irq_domain *domain,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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/* We support standard DT translation */
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if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1];
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return 0;
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}
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if (is_fwnode_irqchip(fwspec->fwnode)) {
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if (fwspec->param_count != 2)
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return -EINVAL;
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1];
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WARN_ON(*type == IRQ_TYPE_NONE);
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return 0;
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}
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return -EINVAL;
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}
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static int ixp4xx_irq_domain_alloc(struct irq_domain *d,
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unsigned int irq, unsigned int nr_irqs,
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void *data)
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{
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struct ixp4xx_irq *ixi = d->host_data;
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irq_hw_number_t hwirq;
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unsigned int type = IRQ_TYPE_NONE;
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struct irq_fwspec *fwspec = data;
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int ret;
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int i;
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ret = ixp4xx_irq_domain_translate(d, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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for (i = 0; i < nr_irqs; i++) {
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/*
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* TODO: after converting IXP4xx to only device tree, set
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* handle_bad_irq as default handler and assume all consumers
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* call .set_type() as this is provided in the second cell in
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* the device tree phandle.
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*/
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irq_domain_set_info(d,
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irq + i,
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hwirq + i,
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&ixi->irqchip,
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ixi,
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handle_level_irq,
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NULL, NULL);
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irq_set_probe(irq + i);
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}
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return 0;
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}
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/*
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* This needs to be a hierarchical irqdomain to work well with the
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* GPIO irqchip (which is lower in the hierarchy)
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*/
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static const struct irq_domain_ops ixp4xx_irqdomain_ops = {
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.translate = ixp4xx_irq_domain_translate,
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.alloc = ixp4xx_irq_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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/**
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* ixp4xx_get_irq_domain() - retrieve the ixp4xx irq domain
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*
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* This function will go away when we transition to DT probing.
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*/
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struct irq_domain *ixp4xx_get_irq_domain(void)
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{
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struct ixp4xx_irq *ixi = &ixirq;
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return ixi->domain;
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}
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EXPORT_SYMBOL_GPL(ixp4xx_get_irq_domain);
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/*
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* This is the Linux IRQ to hwirq mapping table. This goes away when
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* we have DT support as all IRQ resources are defined in the device
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* tree. It will register all the IRQs that are not used by the hierarchical
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* GPIO IRQ chip. The "holes" inbetween these IRQs will be requested by
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* the GPIO driver using . This is a step-gap solution.
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*/
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struct ixp4xx_irq_chunk {
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int irq;
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int hwirq;
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int nr_irqs;
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};
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static const struct ixp4xx_irq_chunk ixp4xx_irq_chunks[] = {
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{
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.irq = 16,
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.hwirq = 0,
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.nr_irqs = 6,
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},
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{
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.irq = 24,
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.hwirq = 8,
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.nr_irqs = 11,
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},
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{
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.irq = 46,
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.hwirq = 30,
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.nr_irqs = 2,
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},
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/* Only on the 436 variants */
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{
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.irq = 48,
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.hwirq = 32,
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.nr_irqs = 10,
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},
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};
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/**
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* ixp4x_irq_setup() - Common setup code for the IXP4xx interrupt controller
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* @ixi: State container
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* @irqbase: Virtual memory base for the interrupt controller
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* @fwnode: Corresponding fwnode abstraction for this controller
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* @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
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*/
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static int __init ixp4xx_irq_setup(struct ixp4xx_irq *ixi,
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void __iomem *irqbase,
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struct fwnode_handle *fwnode,
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bool is_356)
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{
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int nr_irqs;
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ixi->irqbase = irqbase;
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ixi->is_356 = is_356;
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/* Route all sources to IRQ instead of FIQ */
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__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR);
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/* Disable all interrupts */
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__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR);
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if (is_356) {
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/* Route upper 32 sources to IRQ instead of FIQ */
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__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR2);
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/* Disable upper 32 interrupts */
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__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR2);
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nr_irqs = 64;
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} else {
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nr_irqs = 32;
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}
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ixi->irqchip.name = "IXP4xx";
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ixi->irqchip.irq_mask = ixp4xx_irq_mask;
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ixi->irqchip.irq_unmask = ixp4xx_irq_unmask;
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ixi->irqchip.irq_set_type = ixp4xx_set_irq_type;
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ixi->domain = irq_domain_create_linear(fwnode, nr_irqs,
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&ixp4xx_irqdomain_ops,
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ixi);
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if (!ixi->domain) {
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pr_crit("IXP4XX: can not add primary irqdomain\n");
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return -ENODEV;
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}
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set_handle_irq(ixp4xx_handle_irq);
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return 0;
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}
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/**
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* ixp4xx_irq_init() - Function to initialize the irqchip from boardfiles
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* @irqbase: physical base for the irq controller
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* @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
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*/
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void __init ixp4xx_irq_init(resource_size_t irqbase,
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bool is_356)
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{
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struct ixp4xx_irq *ixi = &ixirq;
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void __iomem *base;
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struct fwnode_handle *fwnode;
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struct irq_fwspec fwspec;
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int nr_chunks;
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int ret;
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int i;
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base = ioremap(irqbase, 0x100);
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if (!base) {
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pr_crit("IXP4XX: could not ioremap interrupt controller\n");
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return;
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}
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fwnode = irq_domain_alloc_fwnode(base);
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if (!fwnode) {
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pr_crit("IXP4XX: no domain handle\n");
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return;
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}
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ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);
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if (ret) {
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pr_crit("IXP4XX: failed to set up irqchip\n");
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irq_domain_free_fwnode(fwnode);
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}
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nr_chunks = ARRAY_SIZE(ixp4xx_irq_chunks);
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if (!is_356)
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nr_chunks--;
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/*
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* After adding OF support, this is no longer needed: irqs
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* will be allocated for the respective fwnodes.
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*/
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for (i = 0; i < nr_chunks; i++) {
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const struct ixp4xx_irq_chunk *chunk = &ixp4xx_irq_chunks[i];
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pr_info("Allocate Linux IRQs %d..%d HW IRQs %d..%d\n",
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chunk->irq, chunk->irq + chunk->nr_irqs - 1,
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chunk->hwirq, chunk->hwirq + chunk->nr_irqs - 1);
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fwspec.fwnode = fwnode;
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fwspec.param[0] = chunk->hwirq;
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fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
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fwspec.param_count = 2;
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ret = __irq_domain_alloc_irqs(ixi->domain,
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chunk->irq,
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chunk->nr_irqs,
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NUMA_NO_NODE,
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&fwspec,
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false,
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NULL);
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if (ret < 0) {
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pr_crit("IXP4XX: can not allocate irqs in hierarchy %d\n",
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ret);
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return;
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}
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}
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}
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EXPORT_SYMBOL_GPL(ixp4xx_irq_init);
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#ifdef CONFIG_OF
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int __init ixp4xx_of_init_irq(struct device_node *np,
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struct device_node *parent)
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{
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struct ixp4xx_irq *ixi = &ixirq;
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void __iomem *base;
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struct fwnode_handle *fwnode;
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bool is_356;
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int ret;
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base = of_iomap(np, 0);
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if (!base) {
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pr_crit("IXP4XX: could not ioremap interrupt controller\n");
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return -ENODEV;
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}
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fwnode = of_node_to_fwnode(np);
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/* These chip variants have 64 interrupts */
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is_356 = of_device_is_compatible(np, "intel,ixp43x-interrupt") ||
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of_device_is_compatible(np, "intel,ixp45x-interrupt") ||
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of_device_is_compatible(np, "intel,ixp46x-interrupt");
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ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);
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if (ret)
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pr_crit("IXP4XX: failed to set up irqchip\n");
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return ret;
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}
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IRQCHIP_DECLARE(ixp42x, "intel,ixp42x-interrupt",
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ixp4xx_of_init_irq);
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IRQCHIP_DECLARE(ixp43x, "intel,ixp43x-interrupt",
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ixp4xx_of_init_irq);
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IRQCHIP_DECLARE(ixp45x, "intel,ixp45x-interrupt",
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ixp4xx_of_init_irq);
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IRQCHIP_DECLARE(ixp46x, "intel,ixp46x-interrupt",
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ixp4xx_of_init_irq);
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#endif
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