John Crispin e29b72f5e1 MIPS: Lantiq: Fix interface clock and PCI control register offset ... The XRX200 based SoC have a different register offset for the interface clock and PCI control registers. This patch detects the SoC and sets the register offset at runtime. This make PCI work on the VR9 SoC. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4113/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2012-08-01 17:57:04 +02:00
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Makefile	GPIO: MIPS: lantiq: move gpio-stp and gpio-ebu to the subsystem folder	2012-05-21 14:31:52 +01:00
clk.c	MIPS: lantiq: implement support for clkdev api	2012-05-21 14:31:51 +01:00
dma.c	MIPS: lantiq: convert dma to platform driver	2012-05-21 14:31:51 +01:00
gpio.c	Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus	2012-05-29 18:27:19 -07:00
prom.c	MIPS: lantiq: add xway soc ids	2012-05-15 17:49:23 +02:00
reset.c	OF: MIPS: lantiq: implement OF support	2012-05-21 14:31:49 +01:00
sysctrl.c	MIPS: Lantiq: Fix interface clock and PCI control register offset	2012-08-01 17:57:04 +02:00