505 lines
13 KiB
Plaintext
505 lines
13 KiB
Plaintext
/*
|
|
* Copyright 2013 Greg Ungerer <gerg@uclinux.org>
|
|
* Copyright 2011 Freescale Semiconductor, Inc.
|
|
* Copyright 2011 Linaro Ltd.
|
|
*
|
|
* The code contained herein is licensed under the GNU General Public
|
|
* License. You may obtain a copy of the GNU General Public License
|
|
* Version 2 or later at the following locations:
|
|
*
|
|
* http://www.opensource.org/licenses/gpl-license.html
|
|
* http://www.gnu.org/copyleft/gpl.html
|
|
*/
|
|
|
|
#include "imx50-pinfunc.h"
|
|
#include <dt-bindings/clock/imx5-clock.h>
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
aliases {
|
|
ethernet0 = &fec;
|
|
gpio0 = &gpio1;
|
|
gpio1 = &gpio2;
|
|
gpio2 = &gpio3;
|
|
gpio3 = &gpio4;
|
|
gpio4 = &gpio5;
|
|
gpio5 = &gpio6;
|
|
serial0 = &uart1;
|
|
serial1 = &uart2;
|
|
serial2 = &uart3;
|
|
serial3 = &uart4;
|
|
serial4 = &uart5;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a8";
|
|
reg = <0x0>;
|
|
};
|
|
};
|
|
|
|
tzic: tz-interrupt-controller@0fffc000 {
|
|
compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x0fffc000 0x4000>;
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ckil {
|
|
compatible = "fsl,imx-ckil", "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
ckih1 {
|
|
compatible = "fsl,imx-ckih1", "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <22579200>;
|
|
};
|
|
|
|
ckih2 {
|
|
compatible = "fsl,imx-ckih2", "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
osc {
|
|
compatible = "fsl,imx-osc", "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <24000000>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "simple-bus";
|
|
interrupt-parent = <&tzic>;
|
|
ranges;
|
|
|
|
aips@50000000 { /* AIPS1 */
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x50000000 0x10000000>;
|
|
ranges;
|
|
|
|
spba@50000000 {
|
|
compatible = "fsl,spba-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x50000000 0x40000>;
|
|
ranges;
|
|
|
|
esdhc1: esdhc@50004000 {
|
|
compatible = "fsl,imx50-esdhc";
|
|
reg = <0x50004000 0x4000>;
|
|
interrupts = <1>;
|
|
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
|
|
<&clks IMX5_CLK_DUMMY>,
|
|
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
esdhc2: esdhc@50008000 {
|
|
compatible = "fsl,imx50-esdhc";
|
|
reg = <0x50008000 0x4000>;
|
|
interrupts = <2>;
|
|
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
|
|
<&clks IMX5_CLK_DUMMY>,
|
|
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@5000c000 {
|
|
compatible = "fsl,imx50-uart", "fsl,imx21-uart";
|
|
reg = <0x5000c000 0x4000>;
|
|
interrupts = <33>;
|
|
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
|
|
<&clks IMX5_CLK_UART3_PER_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi1: ecspi@50010000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x50010000 0x4000>;
|
|
interrupts = <36>;
|
|
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
|
|
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi2: ssi@50014000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,imx50-ssi",
|
|
"fsl,imx51-ssi",
|
|
"fsl,imx21-ssi";
|
|
reg = <0x50014000 0x4000>;
|
|
interrupts = <30>;
|
|
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
|
|
dmas = <&sdma 24 1 0>,
|
|
<&sdma 25 1 0>;
|
|
dma-names = "rx", "tx";
|
|
fsl,fifo-depth = <15>;
|
|
status = "disabled";
|
|
};
|
|
|
|
esdhc3: esdhc@50020000 {
|
|
compatible = "fsl,imx50-esdhc";
|
|
reg = <0x50020000 0x4000>;
|
|
interrupts = <3>;
|
|
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
|
|
<&clks IMX5_CLK_DUMMY>,
|
|
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
esdhc4: esdhc@50024000 {
|
|
compatible = "fsl,imx50-esdhc";
|
|
reg = <0x50024000 0x4000>;
|
|
interrupts = <4>;
|
|
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
|
|
<&clks IMX5_CLK_DUMMY>,
|
|
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usbotg: usb@53f80000 {
|
|
compatible = "fsl,imx50-usb", "fsl,imx27-usb";
|
|
reg = <0x53f80000 0x0200>;
|
|
interrupts = <18>;
|
|
clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh1: usb@53f80200 {
|
|
compatible = "fsl,imx50-usb", "fsl,imx27-usb";
|
|
reg = <0x53f80200 0x0200>;
|
|
interrupts = <14>;
|
|
clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
|
|
dr_mode = "host";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh2: usb@53f80400 {
|
|
compatible = "fsl,imx50-usb", "fsl,imx27-usb";
|
|
reg = <0x53f80400 0x0200>;
|
|
interrupts = <16>;
|
|
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
|
dr_mode = "host";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh3: usb@53f80600 {
|
|
compatible = "fsl,imx50-usb", "fsl,imx27-usb";
|
|
reg = <0x53f80600 0x0200>;
|
|
interrupts = <17>;
|
|
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
|
dr_mode = "host";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio1: gpio@53f84000 {
|
|
compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
|
|
reg = <0x53f84000 0x4000>;
|
|
interrupts = <50 51>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 151 28>;
|
|
};
|
|
|
|
gpio2: gpio@53f88000 {
|
|
compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
|
|
reg = <0x53f88000 0x4000>;
|
|
interrupts = <52 53>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>,
|
|
<&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
|
|
<&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
|
|
<&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
|
|
};
|
|
|
|
gpio3: gpio@53f8c000 {
|
|
compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
|
|
reg = <0x53f8c000 0x4000>;
|
|
interrupts = <54 55>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 108 32>;
|
|
};
|
|
|
|
gpio4: gpio@53f90000 {
|
|
compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
|
|
reg = <0x53f90000 0x4000>;
|
|
interrupts = <56 57>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>,
|
|
<&iomuxc 20 140 11>;
|
|
};
|
|
|
|
wdog1: wdog@53f98000 {
|
|
compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
|
|
reg = <0x53f98000 0x4000>;
|
|
interrupts = <58>;
|
|
clocks = <&clks IMX5_CLK_DUMMY>;
|
|
};
|
|
|
|
gpt: timer@53fa0000 {
|
|
compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
|
|
reg = <0x53fa0000 0x4000>;
|
|
interrupts = <39>;
|
|
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
|
|
<&clks IMX5_CLK_GPT_HF_GATE>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
iomuxc: iomuxc@53fa8000 {
|
|
compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
|
|
reg = <0x53fa8000 0x4000>;
|
|
};
|
|
|
|
gpr: iomuxc-gpr@53fa8000 {
|
|
compatible = "fsl,imx50-iomuxc-gpr", "syscon";
|
|
reg = <0x53fa8000 0xc>;
|
|
};
|
|
|
|
pwm1: pwm@53fb4000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
|
|
reg = <0x53fb4000 0x4000>;
|
|
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
|
|
<&clks IMX5_CLK_PWM1_HF_GATE>;
|
|
clock-names = "ipg", "per";
|
|
interrupts = <61>;
|
|
};
|
|
|
|
pwm2: pwm@53fb8000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
|
|
reg = <0x53fb8000 0x4000>;
|
|
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
|
|
<&clks IMX5_CLK_PWM2_HF_GATE>;
|
|
clock-names = "ipg", "per";
|
|
interrupts = <94>;
|
|
};
|
|
|
|
uart1: serial@53fbc000 {
|
|
compatible = "fsl,imx50-uart", "fsl,imx21-uart";
|
|
reg = <0x53fbc000 0x4000>;
|
|
interrupts = <31>;
|
|
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
|
|
<&clks IMX5_CLK_UART1_PER_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@53fc0000 {
|
|
compatible = "fsl,imx50-uart", "fsl,imx21-uart";
|
|
reg = <0x53fc0000 0x4000>;
|
|
interrupts = <32>;
|
|
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
|
|
<&clks IMX5_CLK_UART2_PER_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
src: src@53fd0000 {
|
|
compatible = "fsl,imx50-src", "fsl,imx51-src";
|
|
reg = <0x53fd0000 0x4000>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
clks: ccm@53fd4000{
|
|
compatible = "fsl,imx50-ccm";
|
|
reg = <0x53fd4000 0x4000>;
|
|
interrupts = <0 71 0x04 0 72 0x04>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gpio5: gpio@53fdc000 {
|
|
compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
|
|
reg = <0x53fdc000 0x4000>;
|
|
interrupts = <103 104>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
|
|
};
|
|
|
|
gpio6: gpio@53fe0000 {
|
|
compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
|
|
reg = <0x53fe0000 0x4000>;
|
|
interrupts = <105 106>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
|
|
};
|
|
|
|
i2c3: i2c@53fec000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
|
|
reg = <0x53fec000 0x4000>;
|
|
interrupts = <64>;
|
|
clocks = <&clks IMX5_CLK_I2C3_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@53ff0000 {
|
|
compatible = "fsl,imx50-uart", "fsl,imx21-uart";
|
|
reg = <0x53ff0000 0x4000>;
|
|
interrupts = <13>;
|
|
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
|
|
<&clks IMX5_CLK_UART4_PER_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
aips@60000000 { /* AIPS2 */
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x60000000 0x10000000>;
|
|
ranges;
|
|
|
|
uart5: serial@63f90000 {
|
|
compatible = "fsl,imx50-uart", "fsl,imx21-uart";
|
|
reg = <0x63f90000 0x4000>;
|
|
interrupts = <86>;
|
|
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
|
|
<&clks IMX5_CLK_UART5_PER_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
owire: owire@63fa4000 {
|
|
compatible = "fsl,imx50-owire", "fsl,imx21-owire";
|
|
reg = <0x63fa4000 0x4000>;
|
|
clocks = <&clks IMX5_CLK_OWIRE_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi2: ecspi@63fac000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x63fac000 0x4000>;
|
|
interrupts = <37>;
|
|
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
|
|
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdma: sdma@63fb0000 {
|
|
compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
|
|
reg = <0x63fb0000 0x4000>;
|
|
interrupts = <6>;
|
|
clocks = <&clks IMX5_CLK_SDMA_GATE>,
|
|
<&clks IMX5_CLK_SDMA_GATE>;
|
|
clock-names = "ipg", "ahb";
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
|
|
};
|
|
|
|
cspi: cspi@63fc0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
|
|
reg = <0x63fc0000 0x4000>;
|
|
interrupts = <38>;
|
|
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
|
|
<&clks IMX5_CLK_CSPI_IPG_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@63fc4000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
|
|
reg = <0x63fc4000 0x4000>;
|
|
interrupts = <63>;
|
|
clocks = <&clks IMX5_CLK_I2C2_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@63fc8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
|
|
reg = <0x63fc8000 0x4000>;
|
|
interrupts = <62>;
|
|
clocks = <&clks IMX5_CLK_I2C1_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi1: ssi@63fcc000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
|
|
"fsl,imx21-ssi";
|
|
reg = <0x63fcc000 0x4000>;
|
|
interrupts = <29>;
|
|
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
|
|
dmas = <&sdma 28 0 0>,
|
|
<&sdma 29 0 0>;
|
|
dma-names = "rx", "tx";
|
|
fsl,fifo-depth = <15>;
|
|
status = "disabled";
|
|
};
|
|
|
|
audmux: audmux@63fd0000 {
|
|
compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
|
|
reg = <0x63fd0000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
fec: ethernet@63fec000 {
|
|
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
|
|
reg = <0x63fec000 0x4000>;
|
|
interrupts = <87>;
|
|
clocks = <&clks IMX5_CLK_FEC_GATE>,
|
|
<&clks IMX5_CLK_FEC_GATE>,
|
|
<&clks IMX5_CLK_FEC_GATE>;
|
|
clock-names = "ipg", "ahb", "ptp";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|